基于TMS320F2812 光伏并網(wǎng)發(fā)電模擬裝置PROTEL設(shè)計原理圖+PCB+軟件源碼+WORD論文文檔,硬件采用2層板設(shè)計，PROTEL99SE 設(shè)計的工程文件，包括完整的原理圖和PCB文件，可以做為你的學習設(shè)計參考。 摘要：本文實現(xiàn)了一個基于TMS320F2812 DSP芯片的光伏并網(wǎng)發(fā)電模擬裝置，采用直流穩(wěn)壓源和滑動變阻器來模擬光伏電池。通過TMS320F2812 DSP芯片ADC模塊實時采樣模擬電網(wǎng)電壓的正弦參考信號、光伏電池輸出電壓、負載電壓電流反饋信號等。經(jīng)過數(shù)據(jù)處理后，用PWM模塊產(chǎn)生實時的SPWM 波，控制MOSFET逆變?nèi)珮蜉敵稣也ā１疚挠肞I控制算法實現(xiàn)了輸出信號對給定模擬電網(wǎng)電壓的正弦參考信號的頻率和相位跟蹤，用恒定電壓法實現(xiàn)了光伏電池最大功率點跟蹤（MPPT），從而達到模擬并網(wǎng)的效果。另外本裝置還實現(xiàn)了光伏電池輸出欠壓、負載過流保護功能以及光伏電池輸出欠壓、過流保護自恢復功能、聲光報警功能、孤島效應的檢測、保護與自恢復功能。系統(tǒng)測試結(jié)果表明本設(shè)計完全滿定設(shè)計要求。關(guān)鍵詞：光伏并網(wǎng)，MPPT，DSP Photovoltaic Grid-connected generation simulator Zhangyuxin，Tantiancheng，Xiewuyang(College of Electrical Engineering, Chongqing University)Abstract: This paper presents a photovoltaic grid-connected generation simulator which is based on TMS320F2812 DSP, with a DC voltage source and a variable resistor to simulate the characteristic of photovoltaic cells. We use the internal AD converter to real-time sampling the referenced grid voltage signal, outputting voltage of photovoltaic, feedback outputting voltage and current signal. The PWM module generates SVPWM according to the calculation of the real-time sampling data, to control the full MOSFET inverter bridge output sine wave. We realized that the output voltage of the simulator can track the frequency and phase of the referenced grid voltage with PI regulation, and the maximum photovoltaic power tracking with constant voltage regulation, thereby achieved the purpose of grid-connected simulation. Additionally, this device has the over-voltage and over-current protection, audible and visual alarm, islanding detecting and protection, and it can recover automatically. The testing shows that our design is feasible.Keywords: Photovoltaic Grid-connected，MPPT，DSP 目錄引言 11. 方案論證 11.1. 總體介紹 11.2. 光伏電池模擬裝置 11.3. DC-AC逆變橋 11.4. MOSFET驅(qū)動電路方案 21.5. 逆變電路的變頻控制方案 22. 理論分析與計算 22.1. SPWM產(chǎn)生 22.1.1. 規(guī)則采樣法 22.1.2. SPWM 脈沖的計算公式 32.1.3. SPWM 脈沖計算公式中的參數(shù)計算 32.1.4. TMS320F2812 DSP控制器的事件管理單元 42.1.5. 軟件設(shè)計方法 62.2. MPPT的控制方法與參數(shù)計算 72.3. 同頻、同相的控制方法和參數(shù)計算 8
標簽： tms320f2812 光伏 并網(wǎng)發(fā)電 模擬 protel pcb
上傳時間： 2021-11-02
上傳用戶：
CH340C+RT9013+MINI USB接口板 AD設(shè)計硬件原理圖+PCB文件,ALTIUM設(shè)計的2層板設(shè)計，包括完整的原理圖和PCB文件，主要器件如下：Library Component Count : 12Name Description----------------------------------------------------------------------------------------------------CAP CapacitorCC2640EM CC2630 ModuleCH340 CH340 USB 2 UARTCON11 Connector 11pinsCON12 Connector 12pinsCON3X2 Connector 5*2LED LEDRES ResistorRT9013 RT9013 3.3VSWITCH switch 6*6USB1 USB ConnectorsXDS110-Lte XDS110-Lite Target Interface
標簽： ch340c rt9013 usb 接口 ad設(shè)計
上傳時間： 2021-11-24
上傳用戶：canderile
STM32L475開發(fā)板PDF原理圖+AD集成3D封裝庫+主要器件技術(shù)手冊，集成封裝庫型號列表如下：Library Component Count : 44Name Description----------------------------------------------------------------------------------------------------ANT-2.4G ANT,2.4G,PCB天線ATK-TEST-1*4-2.54mm 測試點ATK_MODULE 單排母,1*6,2.54mmBEEP 3.3V有源蜂鳴器BUTTON_DIP3 撥動開關(guān)SS-12F44C-0402-SMD C-0603-SMD C-CAP-SMD-220uF/10V C-CEP-220uF/16V D-1N4148 Header-1*3-2.54mm 單排針-2.54mmHeader-2*10-2.54mm 雙排針-2.54mmHeader-2*2-2.54mm 雙排針-2.54mmHeader-2*3-2.54mm 雙排針-2.54mmHeader-2*4-2.54mm 雙排座-2.54mmIR-LED 1206紅外發(fā)射管（側(cè)）IR-LF0038GKLL-1 紅外接收管SMDJ-MICRO-USB-5S Micro USB 5.9有柱腳長1.25加長針L-0420-4.7uH 電感,4.7uH,3ALCD-TFT-H13TS38A LCD,TFT,1.3'240*240,禹龍LED-0603-RED 發(fā)光二極管-紅色LED-RGB-1615-0603 RGB,共陽,1615,0603MIC-6022 MICMotor-SMD 電機,SMDPhone-3-M 耳機座,三節(jié)R-0402-SMD 貼片電阻R-0805-SMD 貼片電阻RT9193-3.3S-KEY-SMD-324225 KEY,SMD,324225S8050-SMD SD-MICRO-TF SD,MICRO,TFU-AHT10 Sensor,溫濕度傳感器U-AP3216C Sensor.光照/距離U-AP6181 WIFI Module,SDIOU-ES8388 AUDIO,2-ch DAC,2-ch ADCU-ICM-20608 三軸陀螺儀/三軸加速度計,U-L9110S 電機驅(qū)動,800mAU-RT9013-3.3 LDO,500mAU-STM32F103C8T6 U-STM32L475VET6 MCU,LQFP100,512K FLASH,128K RAMU-W25Q128 SPI FLASH,16MY-12M-SMD 晶振 - 12M貼片Y-3215-32.768K XTAL,3215,32.768KY-3215-8M XTAL,3215,8MHz
上傳時間： 2021-12-15
上傳用戶：
FPGA讀取OV5640攝像頭數(shù)據(jù)并通過VGA或LCD屏顯示輸出的Verilog邏輯源碼Quartus工程文件+文檔說明，F(xiàn)PGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, output cmos_scl, //cmos i2c clock inout cmos_sda, //cmos i2c data input cmos_vsync, //cmos vsync input cmos_href, //cmos hsync refrence,data valid input cmos_pclk, //cmos pxiel clock output cmos_xclk, //cmos externl clock input [7:0] cmos_db, //cmos data output cmos_rst_n, //cmos reset output cmos_pwdn, //cmos power down output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);
上傳時間： 2021-12-18
上傳用戶：
基于FPGA設(shè)計的字符VGA LCD顯示實驗Verilog邏輯源碼Quartus工程文件+文檔說明,通過字符轉(zhuǎn)換工具將字符轉(zhuǎn)換為 8 進制 mif 文件存放到單端口的 ROM IP 核中，再從ROM 中把轉(zhuǎn)換后的數(shù)據(jù)讀取出來顯示到 VGA 上，F(xiàn)PGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue );wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;wire osd_hs;wire osd_vs;wire osd_de;wire[7:0] osd_r;wire[7:0] osd_g;wire[7:0] osd_b;assign vga_out_hs = osd_hs;assign vga_out_vs = osd_vs;assign vga_out_r = osd_r[7:3]; //discard low bit dataassign vga_out_g = osd_g[7:2]; //discard low bit dataassign vga_out_b = osd_b[7:3]; //discard low bit data//generate video pixel clockvideo_pll video_pll_m0( .inclk0 (clk ), .c0 (video_clk ));color_bar color_bar_m0( .clk (video_clk ), .rst (~rst_n ), .hs (video_hs ), .vs (video_vs ), .de (video_de ), .rgb_r (video_r ), .rgb_g (video_g ), .rgb_b (video_b ));osd_display osd_display_m0( .rst_n (rst_n ), .pclk (video_clk ), .i_hs (video_hs ), .i_vs (video_vs ), .i_de (video_de ), .i_data ({video_r,video_g,video_b} ), .o_hs (osd_hs ), .o_vs (osd_vs ), .o_de (osd_de ), .o_data ({osd_r,osd_g,osd_b} ));endmodule
上傳時間： 2021-12-18
上傳用戶：
基于FPGA設(shè)計的sdram讀寫測試實驗Verilog邏輯源碼Quartus工程文件+文檔說明，DRAM選用海力士公司的 HY57V2562 型號,容量為的 256Mbit,采用了 54 引腳的TSOP 封裝, 數(shù)據(jù)寬度都為 16 位, 工作電壓為 3.3V,并丏采用同步接口方式所有的信號都是時鐘信號。FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ps/1psmodule top(input clk,input rst_n,output[1:0] led,output sdram_clk, //sdram clockoutput sdram_cke, //sdram clock enableoutput sdram_cs_n, //sdram chip selectoutput sdram_we_n, //sdram write enableoutput sdram_cas_n, //sdram column address strobeoutput sdram_ras_n, //sdram row address strobeoutput[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank addressoutput[12:0] sdram_addr, //sdram addressinout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24 ; //external memory user interface address widthparameter BUSRT_BITS = 10 ; //external memory user interface burst widthparameter BURST_SIZE = 128 ; //burst sizewire wr_burst_data_req; // from external memory controller,write data request ,before data 1 clockwire wr_burst_finish; // from external memory controller,burst write finish
標簽： fpga sdram verilog quartus
上傳時間： 2021-12-18
上傳用戶：
基于FPGA設(shè)計的vga顯示測試實驗Verilog邏輯源碼Quartus工程文件+文檔說明，F(xiàn)PGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue );wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;assign vga_out_hs = video_hs;assign vga_out_vs = video_vs;assign vga_out_r = video_r[7:3]; //discard low bit dataassign vga_out_g = video_g[7:2]; //discard low bit dataassign vga_out_b = video_b[7:3]; //discard low bit data//generate video pixel clockvideo_pll video_pll_m0( .inclk0(clk), .c0(video_clk));color_bar color_bar_m0( .clk(video_clk), .rst(~rst_n), .hs(video_hs), .vs(video_vs), .de(video_de), .rgb_r(video_r), .rgb_g(video_g), .rgb_b(video_b));endmodule
標簽： fpga vga顯示 verilog quartus
上傳時間： 2021-12-19
上傳用戶：kingwide
FPGA片內(nèi)FIFO讀寫測試Verilog邏輯源碼Quartus工程文件+文檔說明，使用 FPGA 內(nèi)部的 FIFO 以及程序?qū)υ?FIFO 的數(shù)據(jù)讀寫操作。FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////module fifo_test( input clk, //50MHz時鐘 input rst_n //復位信號，低電平有效 );//-----------------------------------------------------------localparam W_IDLE = 1;localparam W_FIFO = 2; localparam R_IDLE = 1;localparam R_FIFO = 2; reg[2:0] write_state;reg[2:0] next_write_state;reg[2:0] read_state;reg[2:0] next_read_state;reg[15:0] w_data; //FIFO寫數(shù)據(jù)wire wr_en; //FIFO寫使能wire rd_en; //FIFO讀使能wire[15:0] r_data; //FIFO讀數(shù)據(jù)wire full; //FIFO滿信號 wire empty; //FIFO空信號 wire[8:0] rd_data_count; wire[8:0] wr_data_count; ///產(chǎn)生FIFO寫入的數(shù)據(jù)always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) write_state <= W_IDLE; else write_state <= next_write_state;endalways@(*)begin case(write_state) W_IDLE: if(empty == 1'b1) //FIFO空， 開始寫FIFO next_write_state <= W_FIFO; else next_write_state <= W_IDLE; W_FIFO: if(full == 1'b1) //FIFO滿 next_write_state <= W_IDLE; else next_write_state <= W_FIFO; default: next_write_state <= W_IDLE; endcaseendassign wr_en = (next_write_state == W_FIFO) ? 1'b1 : 1'b0; always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) w_data <= 16'd0; else if (wr_en == 1'b1) w_data <= w_data + 1'b1; else w_data <= 16'd0; end///產(chǎn)生FIFO讀的數(shù)據(jù)always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) read_state <= R_IDLE; else read_state <= next_read_state;endalways@(*)begin case(read_state) R_IDLE: if(full == 1'b1) //FIFO滿, 開始讀FIFO next_read_state <= R_FIFO; else next_read_state <= R_IDLE; R_FIFO: if(empty == 1'b1)
上傳時間： 2021-12-19
上傳用戶：20125101110
FPGA Verilog HDL設(shè)計溫度傳感器ds18b20溫度讀取并通過lcd1620和8位LED數(shù)碼管顯示的QUARTUS II 12.0工程文件，包括完整的設(shè)計文件.V源碼，可以做為你的學習及設(shè)計參考。module ds18b20lcd1602display ( Clk, Rst, DQ, //18B20數(shù)據(jù)端口 Txd, //串口發(fā)送端口 LCD_Data, //lcd LCD_RS, LCD_RW, LCD_En, SMData, //數(shù)碼管段碼 SMCom //數(shù)碼管位碼 );input Rst,Clk;output Txd,LCD_RS,LCD_En,LCD_RW;inout DQ;output[7:0] LCD_Data;output[7:0] SMData;output[3:0] SMCom;wire DataReady;//測溫完成信號wire [15:0] MeasureResult;//DS18B20測溫結(jié)果reg [15:0] Temperature;//產(chǎn)生LCD的位碼和段碼LCD1602Display Gen_LCD(.resetin(Rst),.clkin(Clk),.Data16bIn(Temperature),.lcd_data(LCD_Data),.lcd_rs(LCD_RS),.lcd_rw(LCD_RW),.lcd_e(LCD_En)/*,.SMCom(SMCom)*/);//DS18B20測溫和發(fā)送 DS18B20 TmpMeasureAndTx(.Rst(Rst),.Clk(Clk),.DQ(DQ),.Txd(Txd),.FinishFlag(DataReady),.Data16b(MeasureResult));//產(chǎn)生數(shù)碼管的位碼和段碼SMDisplay Gen_SM(.Rst(Rst),.
標簽： fpga verilog hdl 溫度傳感器 ds18b20 lcd1620 數(shù)碼顯示
上傳時間： 2022-01-30
上傳用戶：
spi 通信的master部分使用的verilog語言實現(xiàn)，可以做為你的設(shè)計參考。module spi_master(rstb,clk,mlb,start,tdat,cdiv,din, ss,sck,dout,done,rdata); input rstb,clk,mlb,start; input [7:0] tdat; //transmit data input [1:0] cdiv; //clock divider input din; output reg ss; output reg sck; output reg dout; output reg done; output reg [7:0] rdata; //received dataparameter idle=2'b00; parameter send=2'b10; parameter finish=2'b11; reg [1:0] cur,nxt; reg [7:0] treg,rreg; reg [3:0] nbit; reg [4:0] mid,cnt; reg shift,clr;
上傳時間： 2022-02-03
上傳用戶：
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