This book is concerned with integrated circuits and systems for wireless and mobile communications. Circuit techniques and implementation of reconfigurable low-voltage and low-power single-chip CMOS transceivers for multiband and multi- mode universal wireless communications are the focus of the book. Applications encompass both long-range mobile cellular communications (GSM and UMTS) and short-range wireless LANs (IEEE802.11 and Bluetooth). Recent advances in research into transceiver architecture, RF frontend, analogue baseband, RF CAD and automatic testing are reported.
標(biāo)簽： Communication Wireless Circuits Systems and
上傳時(shí)間： 2020-06-01
上傳用戶：shancjb
The explosion in demand for wireless services experienced over the past 20 years has put significant pressure on system designers to increase the capacity of the systems being deployed. While the spectral resource is very scarce and practically exhausted, the biggest possibilities are predicted to be in the areas of spectral reuse by unlicensed users or in exploiting the spatial dimension of the wireless channels. The former approach is now under intense development and is known as the cogni- tive radio approach (Haykin 2005).
標(biāo)簽： Multi-Antenna Wireless Channels Modeling
上傳時(shí)間： 2020-06-01
上傳用戶：shancjb
The planarization technology of Chemical-Mechanical-Polishing (CMP), used for the manufacturing of multi- level metal interconnects for high-density Integrated Circuits (IC), is also readily adaptable as an enabling technology in MicroElectroMechanical Systems (MEMS) fabrication, particularly polysilicon surface micromachining. CMP not only eases the design and manufacturability of MEMS devices by eliminating several photolithographic and film issues generated by severe topography, but also enables far greater flexibility with process complexity and associated designs. T
標(biāo)簽： mechanical polishing Chemical
上傳時(shí)間： 2020-06-06
上傳用戶：shancjb
A power semiconductor module is basically a power circuit of different materials assembled together using hybrid technology, such as semiconduc- tor chip attachment, wire bonding, encapsulation, etc. The materials involved cover a wide range from insulators, conductors, and semiconduc- tors to organics and inorganics. Since these materials all behave differently under various environmental, electrical, and thermal stresses, proper selec- tion of these materials and the assembly processes are critical. In-depth knowledge of the material properties and the processing techniques is there- fore required to build a high-performance and highly reliable power module.
標(biāo)簽： Manufacture Electronic Modules Design Power
上傳時(shí)間： 2020-06-07
上傳用戶：shancjb
stract With global drivers such as better energy consumption, energy efficiency and reduction of greenhouse gases, CO 2 emission reduction has become key in every layer of the value chain. Power Electronics has definitely a role to play in these thrilling challenges. From converters down to compound semiconductors, innovation is leading to breakthrough technologies. Wide BandGap, Power Module Packaging, growth of Electric Vehicle market will game change the overall power electronic industry and supply chain. In this presentation we will review power electronics trends, from technologies to markets.
標(biāo)簽： Electronics Materials Power WBG for
上傳時(shí)間： 2020-06-07
上傳用戶：shancjb
adio Frequency Identification (RFID) is a rapidly developing automatic wireless data-collection technology with a long history.The first multi-bit functional passive RFID systems,with a range of several meters, appeared in the early 1970s, and continued to evolve through the 1980s. Recently, RFID has experienced a tremendous growth,due to developments in integrated circuits and radios, and due to increased interest from the retail industrial and government.
標(biāo)簽： RFID-Enabled Sensors RFID and
上傳時(shí)間： 2020-06-08
上傳用戶：shancjb
Radio frequency identification (RFID) and Wireless sensor networks (WSN) are the two key wireless technologies that have diversified applications in the present and the upcoming systems in this area. RFID is a wireless automated recognition technology which is primarily used to recognize objects or to follow their posi- tion without providing any sign about the physical form of the substance. On the other hand, WSN not only offers information about the state of the substance and environment but also enables multi-hop wireless communications.
標(biāo)簽： Architecture Integrated RFID-WSN
上傳時(shí)間： 2020-06-08
上傳用戶：shancjb
lm75A溫度數(shù)字轉(zhuǎn)換器 FPGA讀寫實(shí)驗(yàn)Verilog邏輯源碼Quartus工程文件+文檔資料,FPGA為CYCLONE4系列中的EP4CE6E22C8. 完整的工程文件，可以做為你的學(xué)習(xí)設(shè)計(jì)參考。LM75A 是一個(gè)使用了內(nèi)置帶隙溫度傳感器和模數(shù)轉(zhuǎn)換技術(shù)的溫度數(shù)字轉(zhuǎn)換器。它也是一個(gè)溫度檢測(cè)器，可提供一個(gè)過熱檢測(cè)輸出。LM75A 包含許多數(shù)據(jù)寄存器：配置寄存器用來存儲(chǔ)器件的某些配置，如器件的工作模式、OS 工作模式、OS 極性和OS 故障隊(duì)列等（在功能描述一節(jié)中有詳細(xì)描述）；溫度寄存器（Temp），用來存儲(chǔ)讀取的數(shù)字溫度；設(shè)定點(diǎn)寄存器（Tos & Thyst），用來存儲(chǔ)可編程的過熱關(guān)斷和滯后限制，器件通過2 線的串行I2C 總線接口與控制器通信。LM75A 還包含一個(gè)開漏輸出（OS），當(dāng)溫度超過編程限制的值時(shí)該輸出有效。LM75A 有3 個(gè)可選的邏輯地址管腳，使得同一總線上可同時(shí)連接8個(gè)器件而不發(fā)生地址沖突。LM75A 可配置成不同的工作條件。它可設(shè)置成在正常工作模式下周期性地對(duì)環(huán)境溫度進(jìn)行監(jiān)控或進(jìn)入關(guān)斷模式來將器件功耗降至最低。OS 輸出有2 種可選的工作模式：OS 比較器模式和OS 中斷模式。OS 輸出可選擇高電平或低電平有效。故障隊(duì)列和設(shè)定點(diǎn)限制可編程，為了激活OS 輸出，故障隊(duì)列定義了許多連續(xù)的故障。溫度寄存器通常存放著一個(gè)11 位的二進(jìn)制數(shù)的補(bǔ)碼，用來實(shí)現(xiàn)0.125℃的精度。這個(gè)高精度在需要精確地測(cè)量溫度偏移或超出限制范圍的應(yīng)用中非常有用。正常工作模式下，當(dāng)器件上電時(shí)，OS 工作在比較器模式，溫度閾值為80℃，滯后75℃，這時(shí)，LM75A就可用作一個(gè)具有以上預(yù)定義溫度設(shè)定點(diǎn)的獨(dú)立的溫度控制器。module LM75_SEG_LED ( //input input sys_clk ,input sys_rst_n ,inout sda_port ,//output output wire seg_c1 ,output wire seg_c2 ,output wire seg_c3 ,output wire seg_c4 ,output reg seg_a ,output reg seg_b ,output reg seg_c ,output reg seg_e ,output reg seg_d ,output reg seg_f ,output reg seg_g ,output reg seg_h , output reg clk_sclk );//parameter define parameter WIDTH = 8;parameter SIZE = 8;//reg define reg [WIDTH-1:0] counter ;reg [9:0] counter_div ;reg clk_50k ;reg clk_200k ;reg sda ;reg enable ;
標(biāo)簽： lm75a 數(shù)字轉(zhuǎn)換器 fpga verilog
上傳時(shí)間： 2021-10-27
上傳用戶：
FPGA采樣AD9238數(shù)據(jù)并通過VGA波形顯示例程 Verilog邏輯源碼Quartus工程文件+文檔說明,FPGA型號(hào)Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。ADC 模塊型號(hào)為 AN9238，最大采樣率 65Mhz，精度為12 位。實(shí)驗(yàn)中把 AN9238 的 2 路輸入以波形方式在 HDMI 上顯示出來，我們可以用更加直觀的方式觀察波形，是一個(gè)數(shù)字示波器雛形。module top( input clk, input rst_n, output ad9238_clk_ch0, output ad9238_clk_ch1, input[11:0] ad9238_data_ch0, input[11:0] ad9238_data_ch1, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue);wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;wire grid_hs;wire grid_vs;wire grid_de;wire[7:0] grid_r;wire[7:0] grid_g;wire[7:0] grid_b;wire wave0_hs;wire wave0_vs;wire wave0_de;wire[7:0] wave0_r;wire[7:0] wave0_g;wire[7:0] wave0_b;wire wave1_hs;wire wave1_vs;wire wave1_de;wire[7:0] wave1_r;wire[7:0] wave1_g;wire[7:0] wave1_b;wire adc_clk;wire adc0_buf_wr;wire[10:0] adc0_buf_addr;wire[7:0] adc0_bu
上傳時(shí)間： 2021-10-27
上傳用戶：qingfengchizhu
FPGA讀寫SD卡讀取BMP圖片通過LCD顯示例程實(shí)驗(yàn) Verilog邏輯源碼Quartus工程文件+文檔說明,FPGA型號(hào)Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。1 實(shí)驗(yàn)簡(jiǎn)介在前面的實(shí)驗(yàn)中我們練習(xí)了 SD 卡讀寫，VGA 視頻顯示等例程，本實(shí)驗(yàn)將 SD 卡里的 BMP 圖片讀出，寫入到外部存儲(chǔ)器，再通過 VGA、LCD 等顯示。本實(shí)驗(yàn)如果通過液晶屏顯示，需要有液晶屏模塊。2 實(shí)驗(yàn)原理在前面的實(shí)驗(yàn)中我們?cè)?VGA、LCD 上顯示的是彩條，是 FPGA 內(nèi)部產(chǎn)生的數(shù)據(jù)，本實(shí)驗(yàn)將彩條替換為 SD 內(nèi)的 BMP 圖片數(shù)據(jù)，但是 SD 卡讀取速度遠(yuǎn)遠(yuǎn)不能滿足顯示速度的要求，只能先寫入外部高速 RAM，再讀出后給視頻時(shí)序模塊顯示module top( input clk, input rst_n, input key1, output [5:0] seg_sel, output [7:0] seg_data, output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sd_ncs, //SD card chip select (SPI mode) output sd_dclk, //SD card clock output sd_mosi, //SD card controller data output input sd_miso, //SD card controller data input output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24
標(biāo)簽： fpga
上傳時(shí)間： 2021-10-27
上傳用戶：
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