n recent years, there have been many books published on power system optimization. Most of these books do not cover applications of artifi cial intelligence based methods. Moreover, with the recent increase of artifi cial intelligence applications in various fi elds, it is becoming a new trend in solving optimization problems in engineering in general due to its advantages of being simple and effi cient in tackling complex problems. For this reason, the application of artifi cial intelligence in power systems has attracted the interest of many researchers around the world during the last two decades. This book is a result of our effort to provide information on the latest applications of artifi cial intelligence to optimization problems in power systems before and after deregulation.
標簽： Intelligence Artificial System Power in
上傳時間： 2020-06-10
上傳用戶：shancjb
A kinematically redundant manipulator is a serial robotic arm that has more independently driven joints than are necessary to define the desired pose (position and orientation) of its end-effector. With this definition, any planar manipulator (a manipulator whose end-effector motion is restrained in a plane) with more than three joints is a redundant manipulator. Also, a manipulator whose end-effector can accept aspatialposeisaredundant manipulator ifithas morethan sixindependently driven joints. For example, the manipulator shown in Fig. 1.1 has two 7-DOF arms mounted on a torso with three degrees of freedom (DOFs). This provides 10 DOFs for each arm. Since the end-effector of each arm can have a spatial motion with six DOFs, the arms are redundant.
標簽： Autonomous Modeling Planning Robots Path
上傳時間： 2020-06-10
上傳用戶：shancjb
Pattern recognition has its origins in engineering, whereas machine learning grew out of computer science. However, these activities can be viewed as two facets of the same field, and together they have undergone substantial development over the past ten years. In particular, Bayesian methods have grown from a specialist niche to become mainstream, while graphical models have emerged as a general framework for describing and applying probabilistic models. Also, the practical applicability of Bayesian methods has been greatly enhanced through the development of a range of approximate inference algorithms such as variational Bayes and expectation propa- gation. Similarly, new models based on kernels have had significant impact on both algorithms and applications.
標簽： Bishop-Pattern-Recognition-and-Ma chine-Learning
上傳時間： 2020-06-10
上傳用戶：shancjb
Current field forecast verification measures are inadequate, primarily because they compress the comparison between two complex spatial field processes into one number. Discrete wavelet transforms (DWTs) applied to analysis and contemporaneous forecast fields prove to be an insightful approach to verification problems. DWTs allow both filtering and compact physically interpretable partitioning of fields. These techniques are used to reduce or eliminate noise in the verification process and develop multivariate measures of field forecasting performance that are shown to improve upon existing verification procedures.
標簽： field forecast verification
上傳時間： 2020-07-22
上傳用戶：
An Arduino core for the ATmega328, ATmega168, ATmega88, ATmega48 and ATmega8, all running a [custom version of Optiboot for increased functionality](#write-to-own-flash). This core requires at least Arduino IDE v1.6.2, where v1.8.5+ is recommended. <br/> **This core gives you two extra IO pins if you're using the internal oscillator!** PB6 and PB7 is mapped to [Arduino pin 20 and 21](#pinout).<br/> If you're into "generic" AVR programming, I'm happy to tell you that all relevant keywords are being highlighted by the IDE through a separate keywords file. Make sure to test the [example files](https://github.com/MCUdude/MiniCore/tree/master/avr/libraries/AVR_examples/examples) (File > Examples > AVR C code examples). Try writing a register name, <i>DDRB</i> for instance, and see for yourself!
標簽： MiniCore
上傳時間： 2021-02-22
上傳用戶：
%this is an example demonstrating the Radial Basis Function %if you select a RBF that supports it (Gausian, or 1st or 3rd order %polyharmonic spline), this also calculates a line integral between two %points.
上傳時間： 2021-07-02
上傳用戶：19800358905
FPGA讀寫SD卡讀取BMP圖片通過LCD顯示例程實驗 Verilog邏輯源碼Quartus工程文件+文檔說明,FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。1 實驗簡介在前面的實驗中我們練習了 SD 卡讀寫，VGA 視頻顯示等例程，本實驗將 SD 卡里的 BMP 圖片讀出，寫入到外部存儲器，再通過 VGA、LCD 等顯示。本實驗如果通過液晶屏顯示，需要有液晶屏模塊。2 實驗原理在前面的實驗中我們在 VGA、LCD 上顯示的是彩條，是 FPGA 內部產生的數據，本實驗將彩條替換為 SD 內的 BMP 圖片數據，但是 SD 卡讀取速度遠遠不能滿足顯示速度的要求，只能先寫入外部高速 RAM，再讀出后給視頻時序模塊顯示module top( input clk, input rst_n, input key1, output [5:0] seg_sel, output [7:0] seg_data, output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sd_ncs, //SD card chip select (SPI mode) output sd_dclk, //SD card clock output sd_mosi, //SD card controller data output input sd_miso, //SD card controller data input output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24
標簽： fpga
上傳時間： 2021-10-27
上傳用戶：
This texts contemporary approach focuses on the concepts of linear control systems, rather than computational mechanics. Straightforward coverage includes an integrated treatment of both classical and modern control system methods. The text emphasizes design with discussions of problem formulation, design criteria, physical constraints, several design methods, and implementation of compensators.Discussions of topics not found in other texts--such as pole placement, model matching and robust tracking--add to the texts cutting-edge presentation. Students will appreciate the applications and discussions of practical aspects, including the leading problem in developing block diagrams, noise, disturbances, and plant perturbations. State feedback and state estimators are designed using state variable equations and transfer functions, offering a comparison of the two approaches. The incorporation of MATLAB throughout the text helps students to avoid time-consuming computation and concentrate on control system design and analysis
標簽： 控制系統
上傳時間： 2021-12-15
上傳用戶：
FPGA讀取OV5640攝像頭數據并通過VGA或LCD屏顯示輸出的Verilog邏輯源碼Quartus工程文件+文檔說明，FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, output cmos_scl, //cmos i2c clock inout cmos_sda, //cmos i2c data input cmos_vsync, //cmos vsync input cmos_href, //cmos hsync refrence,data valid input cmos_pclk, //cmos pxiel clock output cmos_xclk, //cmos externl clock input [7:0] cmos_db, //cmos data output cmos_rst_n, //cmos reset output cmos_pwdn, //cmos power down output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);
上傳時間： 2021-12-18
上傳用戶：
基于FPGA設計的sdram讀寫測試實驗Verilog邏輯源碼Quartus工程文件+文檔說明，DRAM選用海力士公司的 HY57V2562 型號,容量為的 256Mbit,采用了 54 引腳的TSOP 封裝, 數據寬度都為 16 位, 工作電壓為 3.3V,并丏采用同步接口方式所有的信號都是時鐘信號。FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ps/1psmodule top(input clk,input rst_n,output[1:0] led,output sdram_clk, //sdram clockoutput sdram_cke, //sdram clock enableoutput sdram_cs_n, //sdram chip selectoutput sdram_we_n, //sdram write enableoutput sdram_cas_n, //sdram column address strobeoutput sdram_ras_n, //sdram row address strobeoutput[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank addressoutput[12:0] sdram_addr, //sdram addressinout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24 ; //external memory user interface address widthparameter BUSRT_BITS = 10 ; //external memory user interface burst widthparameter BURST_SIZE = 128 ; //burst sizewire wr_burst_data_req; // from external memory controller,write data request ,before data 1 clockwire wr_burst_finish; // from external memory controller,burst write finish
標簽： fpga sdram verilog quartus
上傳時間： 2021-12-18
上傳用戶：
