本文利用Verilog HDL 語言自頂向下的設計方法設計多功能數字鐘，突出了其作為硬件描述語言的良好的可讀性、可移植性和易理解等優點，并通過Altera QuartusⅡ 4.1 和ModelSim SE 6.0 完成綜合、仿真。此程序通過下載到FPGA 芯片后，可應用于實際的數字鐘顯示中。 關鍵詞：Verilog HDL；硬件描述語言；FPGA Abstract: In this paper, the process of designing multifunctional digital clock by the Verilog HDL top-down design method is presented, which has shown the readability, portability and easily understanding of Verilog HDL as a hard description language. Circuit synthesis and simulation are performed by Altera QuartusⅡ 4.1 and ModelSim SE 6.0. The program can be used in the truly digital clock display by downloading to the FPGA chip. Keywords: Verilog HDL；hardware description language；FPGA
上傳時間： 2013-11-10
上傳用戶：hz07104032
研究一種基于TMS320F28335 DSP（Digital Signal Processor）的全數字飛行器控制系統的硬件設計，分析了其結構組成：主控制器電路、舵面位置檢測電路和通訊等硬件電路設計。經過多次試驗調試，所設計的硬件系統可以滿足飛行器性能要求。
上傳時間： 2013-10-10
上傳用戶：z1191176801
The power of programmability gives industrial automation designers a highly efficient， cost-effective alternative to traditional motor control units （MCUs）。 The parallel-processing power， fast computational speeds， and connectivity versatility of Xilinx® FPGAs can accelerate the implementation of advanced motor control algorithms such as Field Oriented Control （FOC）。 Additionally， Xilinx devices lower costs with greater on-chip integration of system components and shorten latencies with high-performance digital signal processing （DSP） that can tackle compute-intensive functions such as PID Controller， Clark/Park transforms， and Space Vector PWM. The Xilinx Spartan®-6 FPGA Motor Control Development Kit gives designers an ideal starting point for evaluating time-saving， proven， motor-control reference designs. The kit also shortens the process of developing custom control capabilities， with integrated peripheral functions （Ethernet， PowerLink， and PCI® Express）， a motor-control FPGA mezzanine card （FMC） with built-in Texas Instruments motor drivers and high-precision Delta-Sigma modulators， and prototyping support for evaluating alternative front-end circuitry.
上傳時間： 2013-10-28
上傳用戶：wujijunshi
Abstract: As industrial control systems (ICSs) have become increasingly connected and use more off-the-shelfcomponents, new vulnerabilities to cyber attacks have emerged. This tutorial looks at three types of ICSs:programmable logic controllers (PLCs), supervisory control and data acquisition (SCADA) systems, anddistributed control systems (DCSs), and then discusses security issues and remedies. This document alsoexplains the benefits and limitations of two cryptographic solutions (digital signatures and encryption) andelaborates on the reasons for using security ICs in an ICS to support cryptography.
上傳時間： 2013-10-09
上傳用戶：woshinimiaoye
The data plane of the reference design consists of a configurable multi-channel XBERT modulethat generates and checks high-speed serial data transmitted and received by the MGTs. Eachchannel in the XBERT module consists of two MGTs (MGTA and MGTB), which physicallyoccupy one MGT tile in the Virtex-4 FPGA. Each MGT has its own pattern checker, but bothMGTs in a channel share the same pattern generator. Each channel can load a differentpattern. The MGT serial rate depends on the reference clock frequency and the internal PMAdivider settings. The reference design can be scaled anywhere from one channel (two MGTs)to twelve channels (twenty-four MGTs).
上傳時間： 2013-12-25
上傳用戶：jkhjkh1982
The high defi nition multimedia interface (HDMI) is fastbecoming the de facto standard for passing digitalaudio and video data in home entertainment systems.This standard includes an I2C type bus called a displaydata channel (DDC) that is used to pass extended digitalinterface data (EDID) from the sinkdevice (such as adigital TV) to the source device (such as a digital A/Vreceiver). EDID includes vital information on the digitaldata formats that the sink device can accept. The HDMIspecifi cation requires that devices have less than 50pFof input capacitance on their DDC bus lines, which canbe very diffi cult to meet. The LTC®4300A’s capacitancebuffering feature allows devices to pass the HDMI DDCinput capacitance compliance test with ease.
上傳時間： 2013-11-21
上傳用戶：tian126vip
ACPR (adjacent channel power ratio), AltCPR (alternatechannel power ratio), and noise are important performancemetrics for digital communication systems thatuse, for example, WCDMA (wideband code division multipleaccess) modulation. ACPR and AltCPR are bothmeasures of spectral regrowth. The power in the WCDMAcarrier is measured using a 5MHz measurement bandwidth;see Figure 1. In the case of ACPR, the total powerin a 3.84MHz bandwidth centered at 5MHz (the carrierspacing) away from the center of the outermost carrier ismeasured and compared to the carrier power. The resultis expressed in dBc. For AltCPR, the procedure is thesame, except we center the measurement 10MHz awayfrom the center of the outermost carrier.
上傳時間： 2013-11-02
上傳用戶：maricle
ARM通訊 H-JTAG 是一款簡單易用的的調試代理軟件，功能和流行的MULTI-ICE 類似。H-JTAG 包括兩個工具軟件：H-JTAG SERVER 和H-FLASHER。其中，H-JTAG SERVER 實現調試代理的功能，而H-FLASHER則實現了FLASH 燒寫的功能。H-JTAG 的基本結構如下圖1-1所示?！ -JTAG支持所有基于ARM7 和ARM9的芯片的調試，并且支持大多數主流的ARM調試軟件，如ADS、RVDS、IAR 和KEIL。通過靈活的接口配置，H-JTAG 可以支持WIGGLER，SDT-JTAG 和用戶自定義的各種JTAG 調試小板。同時，附帶的H-FLASHER 燒寫軟件還支持常用片內片外FLASH 的燒寫。使用H-JTAG，用戶能夠方便的搭建一個簡單易用的ARM 調試開發平臺。H-JTAG 的功能和特定總結如下： 1. 支持 RDI 1.5.0 以及 1.5.1； 2. 支持所有ARM7 以及 ARM9 芯片； 3. 支持 THUMB 以及ARM 指令； 4. 支持 LITTLE-ENDIAN 以及 BIG-ENDIAN； 5. 支持 SEMIHOSTING； 6. 支持 WIGGLER， SDT-JTAG和用戶自定義JTAG調試板； 7. 支持 WINDOWS 9.X/NT/2000/XP； 8．支持常用FLASH 芯片的編程燒寫； 9. 支持LPC2000 和AT91SAM 片內FLASH 的自動下載；
上傳時間： 2013-11-19
上傳用戶：水中浮云
XMail is an Internet and intranet mail server featuring an SMTP server, POP3 server, finger server, multiple domains, no need for users to have a real system account, SMTP relay checking, RBL/RSS/ORBS/DUL and custom ( IP based and address based ) spam protection, SMTP authentication ( PLAIN LOGIN CRAM-MD5 POP3-before-SMTP and custom ), a POP3 account syncronizer with external POP3 accounts, account aliases, domain aliases, custom mail processing, direct mail files delivery, custom mail filters, mailing lists, remote administration, custom mail exchangers, logging, and multi-platform code. XMail sources compile under GNU/Linux, FreeBSD, OpenBSD, NetBSD, OSX, Solaris and NT/2K/XP.
標簽： server featuring Internet intranet
上傳時間： 2015-01-12
上傳用戶：asddsd
來自《VC6.0可視化編程》的源碼，適用于初學者。 這是第一章，關于multi windows 的代碼
上傳時間： 2013-12-20
上傳用戶：TF2015
