pic單片機資料 請注意以下有關Microchip 器件代碼保護功能的要點：• Microchip的產品均達到Microchip 數據手冊中所述的技術指標。• Microchip確信：在正常使用的情況下， Microchip 系列產品是當今市場上同類產品中最安全的產品之一。• 目前，仍存在著惡意、甚至是非法破壞代碼保護功能的行為。就我們所知，所有這些行為都不是以Microchip 數據手冊中規定的操作規范來使用Microchip 產品的。這樣做的人極可能侵犯了知識產權。• Microchip愿與那些注重代碼完整性的客戶合作。• Microchip或任何其它半導體廠商均無法保證其代碼的安全性。代碼保護并不意味著我們保證產品是“牢不可破”的。代碼保護功能處于持續發展中。Microchip 承諾將不斷改進產品的代碼保護功能。任何試圖破壞Microchip 代碼保護功能的行為均可視為違反了《數字器件千年版權法案（Digital Millennium Copyright Act）》。如果這種行為導致他人在未經授權的情況下，能訪問您的軟件或其它受版權保護的成果，您有權依據該法案提起訴訟，從而制止這種行為。
上傳時間： 2013-10-19
上傳用戶：nunnzhy
dsp開發工具 請注意以下有關Microchip 器件代碼保護功能的要點： • Microchip 的產品均達到Microchip 數據手冊中所述的技術指標。 • Microchip 確信：在正常使用的情況下， Microchip 系列產品是當今市場上同類產品中最安全的產品之一。 • 目前，仍存在著惡意、甚至是非法破壞代碼保護功能的行為。就我們所知，所有這些行為都不是以Microchip 數據手冊中規定的 操作規范來使用Microchip 產品的。這樣做的人極可能侵犯了知識產權。 • Microchip 愿與那些注重代碼完整性的客戶合作。 • Microchip 或任何其他半導體廠商均無法保證其代碼的安全性。代碼保護并不意味著我們保證產品是“牢不可破”的。 代碼保護功能處于持續發展中。Microchip 承諾將不斷改進產品的代碼保護功能。任何試圖破壞Microchip 代碼保護功能的行為均可視 為違反了《數字器件千年版權法案（Digital Millennium Copyright Act）》。如果這種行為導致他人在未經授權的情況下，能訪問您的 軟件或其他受版權保護的成果，您有權依據該法案提起訴訟，從而制止這種行為。
上傳時間： 2014-12-28
上傳用戶：123312
針對使用硬件描述語言進行設計存在的問題，提出一種基于FPGA并采用DSP Builder作為設計工具的數字信號處理器設計方法。并按照Matlab/Simulink/DSP Builder/QuartusⅡ設計流程，設計了一個12階FIR 低通數字濾波器，通過Quartus 時序仿真及嵌入式邏輯分析儀SignalTapⅡ硬件測試對設計進行了驗證。結果表明，所設計的FIR 濾波器功能正確，性能良好。 Abstract: Aiming at the problems in designing DSP using HDL，a method of designing DSP based on FPGA which using DSP Builder as designed tool is pointed out.A 12-order low-pass FIR digital filter was designed according to the process of Matlab/Simulink/DSP Builder/QuartusⅡ, and the design was verified by the timing simulation based on QuartusⅡand practical test based on SignalTapⅡ. The result shows the designed filter is correct in function and good in performance.
上傳時間： 2013-11-17
上傳用戶：lo25643
在綜合分析諧波勵磁無刷同步發電機勵磁控制系統的基礎上,對其勵磁控制策略進行了研究,開發了一套基于DSP( TMS320F2812) 控制的新型柴油發電機勵磁控制系統,該系統采用參數自適應模糊PID 控制勵磁,選用交流采樣方式實時檢測各信號的瞬時特性,系統仿真結果以及在1 臺25 kW 工頻柴油發電機上的試驗結果證明了該控制器具有較好的電壓調節特性,系統穩態和暫態性能完全滿足發電機對勵磁系統的要求。關鍵詞:勵磁調節;模糊PID 控制;數字信號處理器;交流采樣 Abstract :According to the general analysis of the excitation cont rol system of the harmonious wave excitation brushless synchronous generator and it s characteristics ,a new type of diesel generator excitation cont rol system based on DSP( TMS320F2812) was designed. An adaptive fuzzy PID cont rol of excitation is used in this system. To detect the t ransient characteristics of the signals in a timely manner ,AC sampling was applied.The system simulation result s and the testing result s f rom a 25 kW diesel generator (50 Hz) can prove that the voltage regulation characteristics of the excitation cont rol system are very well ,and both the steadyOstate performance and the t ransient performance of the generator are also good.Key words :excitation cont rol ;fuzzy PID cont rol ;digital signal processor (DSP) ;AC sampling
上傳時間： 2013-10-29
上傳用戶：fxf126@126.com
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽： UltraScale Xilinx 架構
上傳時間： 2013-11-13
上傳用戶：瓦力瓦力hong
Designing withProgrammable Logicin an Analog WorldProgrammable logic devicesrevolutionized digital design over 25years ago, promising designers a blankchip to design literally any functionand program it in the field. PLDs canbe low-logic density devices that usenonvolatile sea-of-gates cells calledcomplex programmable logic devices(CPLDs) or they can be high-densitydevices based on SRAM look-up tables
標簽： Solutions Analog Xilinx FPGAs
上傳時間： 2013-11-01
上傳用戶：a67818601
The SDI standards are the predominant standards for uncompressed digital videointerfaces in the broadcast studio and video production center. The first SDI standard,SD-SDI, allowed standard-definition digital video to be transported over the coaxial cableinfrastructure initially installed in studios to carry analog video. Next, HD-SDI wasto support high-definition video. Finally, dual link HD-SDI and 3G-SDIdoubled the bandwidth of HD-SDI to support 1080p (50 Hz and 60 Hz) and other videoformats requiring more bandwidth than HD-SDI provides.
上傳時間： 2013-10-08
上傳用戶：yjj631
為了在CDMA系統中更好地應用QDPSK數字調制方式，在分析四相相對移相（QDPSK)信號調制解調原理的基礎上，設計了一種QDPSK調制解調電路，它包括串并轉換、差分編碼、四相載波產生和選相、相干解調、差分譯碼和并串轉換電路。在MAX+PLUSⅡ軟件平臺上，進行了編譯和波形仿真。綜合后下載到復雜可編程邏輯器件EPM7128SLC84-15中，測試結果表明，調制電路能正確選相，解調電路輸出數據與QDPSK調制輸入數據完全一致，達到了預期的設計要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
上傳時間： 2014-01-13
上傳用戶：qoovoop
為了響應國家工業和信心產業部[2009]666號文件我國數字對講機實現模擬轉數字化的要求，并且為了方便企業生產和調試、降低成本的目的。采用國產基帶芯片SCT3918設計了一款適應我國國情的數字對講機CDMR（China Digital Mobile Radio），在實驗室內做了射頻技術指標測試、音頻技術指標測試、可靠性測試，實驗結果表明射頻技術指標符合[2009]666號文件要求，音頻技術指標符合《移動通信調頻無線電話機通用技術條件》，設計符合我國對講機模擬轉數字的政策、適合我國的國情、便于企業生產和調試。
上傳時間： 2013-10-18
上傳用戶：caozhizhi
Abstract: Many industrial/scientific/medical (ISM) band radio frequency (RF) receivers use an external Sallen-Key datafilter and a data slicer to generate the baseband digital output. This tutorial describes the ISM-RF Baseband Calculator,which can be used to calculate the filter capacitor values and the data slicer RC components, while providing a visualexample of the baseband signals.
上傳時間： 2013-11-04
上傳用戶：jkhjkh1982
