中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽： UltraScale Xilinx 架構
上傳時間： 2013-11-21
上傳用戶：wxqman
介紹高速電路的設計
標簽： High-speed Digital Design 高速數字
上傳時間： 2013-12-02
上傳用戶：wentianyou
Nios II定制指令用戶指南：With the Altera Nios II embedded processor, you as the system designer can accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. Using custom instructions, you can reduce a complex sequence of standard instructions to a single instruction implemented in hardware. You can use this feature for a variety of applications, for example, to optimize software inner loops for digital signal processing (DSP), packet header processing, and computation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphical user interface (GUI) used to add up to 256 custom instructions to the Nios II processor. The custom instruction logic connects directly to the Nios II arithmetic logic unit (ALU) as shown in Figure 1–1.
上傳時間： 2013-10-12
上傳用戶：kang1923
Arduino 是一塊基于開放原始代碼的Simple i/o 平臺，并且具有使用類似java,C 語言的開發環境。讓您可以快速 使用Arduino 語言與Flash 或Processing…等軟件，作出互動作品。Arduino 可以使用開發完成的電子元件例如Switch 或Sensors 或其他控制器、ＬＥＤ、步進電機或其他輸出裝置。Arduino 也可以獨立運作成為一個可以跟軟件溝通的平臺，例如說：flash processing Max/MSP VVVV 或其他互動軟件… Arduino 開發ＩＤＥ界面基于開放原始碼原則，可以讓您免費下載使用開發出更多令人驚奇的互動作品。 什么是Roboduino? DFRduino 與Arduino 完全兼容，只是在原來的基礎上作了些改進。Arduino 的IO 使用的孔座，做互動作品需要面包板和針線搭配才能進行，而DFRduino 的IO 使用針座，使用我們的杜邦線就可以直接把各種傳感器連接到DFRduino 上。 特色描述 1． 開放原始碼的電路圖設計，程式開發界面免費下載，也可依需求自己修改!! 2． DFRduino 可使用ISP 下載線，自我將新的IC 程序燒入「bootloader」； 3． 可依據官方電路圖，簡化DFRduino 模組，完成獨立云作的微處理控制器； 4． 可簡單地與傳感器、各式各樣的電子元件連接(如：紅外線,超聲波,熱敏電阻,光敏電阻,伺服電機等)； 5． 支援多樣的互動程式 如: Flash,Max/Msp,VVVV,PD,C,Processing 等； 6． 使用低價格的微處理控制器(ATMEGA168V-10PI)； 7． USB 接口，不需外接電源，另外有提供9VDC 輸入接口； 8． 應用方面，利用DFRduino，突破以往只能使用滑鼠，鍵盤，CCD 等輸入的裝置的互動內容，可以更簡單地達成單人或多人游戲互動。 性能描述 1． Digital I/O 數字輸入/輸出端共 0~13。 2． Analog I/O 模擬輸入/輸出端共 0~5。 3． 支持USB 接口協議及供電(不需外接電源)。 4． 支持ISP 下載功能。 5． 支持單片機TX/RX 端子。 6． 支持USB TX/RX 端子。 7． 支持AREF 端子。 8． 支持六組PWM 端子(Pin11,Pin10,Pin9，Pin6,Pin5,Pin3)。 9． 輸入電壓：接上USB 時無須外部供電或外部5V~9V DC 輸入。 10．輸出電壓：5V DC 輸出和3.3V DC 輸出 和外部電源輸入。 11．采用Atmel Atmega168V-10PI 單片機。 12．DFRduino 大小尺寸：寬70mm X 高54mm。 Arduino開發板圖片
上傳時間： 2013-10-30
上傳用戶：wangzhen1990
Designing withProgrammable Logicin an Analog WorldProgrammable logic devicesrevolutionized digital design over 25years ago, promising designers a blankchip to design literally any functionand program it in the field. PLDs canbe low-logic density devices that usenonvolatile sea-of-gates cells calledcomplex programmable logic devices(CPLDs) or they can be high-densitydevices based on SRAM look-up tables
標簽： Solutions Analog Xilinx FPGAs
上傳時間： 2013-11-07
上傳用戶：suicone
Digital cameras have become increasingly popular over the last few years. Digital imagingtechnology has grown to new markets including cellular phones and PDA devices. With thediverse marketplace, a variety of imaging technology must be available. Imaging technologyhas expanded to include both charge-coupled device (CCD) and CMOS image sensors.
標簽： CoolRunner-II XAPP CPLD 390
上傳時間： 2013-10-16
上傳用戶：18710733152
MP3 portable players are the trend in music-listening technology. These players do not includeany mechanical movements, thereby making them ideal for listening to music during any type ofactivity. MP3 is a digital compression technique based on MPEG Layer 3 which stores music ina lot less space than current CD technology. Software is readily available to create MP3 filesfrom an existing CD, and the user can then download these files into a portable MP3 player tobe enjoyed in almost any environment.
上傳時間： 2013-11-23
上傳用戶：nanxia
The SDI standards are the predominant standards for uncompressed digital videointerfaces in the broadcast studio and video production center. The first SDI standard,SD-SDI, allowed standard-definition digital video to be transported over the coaxial cableinfrastructure initially installed in studios to carry analog video. Next, HD-SDI wasto support high-definition video. Finally, dual link HD-SDI and 3G-SDIdoubled the bandwidth of HD-SDI to support 1080p (50 Hz and 60 Hz) and other videoformats requiring more bandwidth than HD-SDI provides.
上傳時間： 2013-12-08
上傳用戶：liansi
Finite state machines are widely used in digital circuit designs. Generally, when designing a state machine using an HDL, the synthesis tools will optimize away all states that cannot be reached and generate a highly optimized circuit. Sometimes, however, the optimization is not acceptable. For example, if the circuit powers up in an invalid state, or the circuit is in an extreme working environment and a glitch sends it into an undesired state, the circuit may never get back to its normal operating condition.
標簽： Creating Machines Mentor State
上傳時間： 2013-11-02
上傳用戶：xauthu
為了在CDMA系統中更好地應用QDPSK數字調制方式，在分析四相相對移相（QDPSK)信號調制解調原理的基礎上，設計了一種QDPSK調制解調電路，它包括串并轉換、差分編碼、四相載波產生和選相、相干解調、差分譯碼和并串轉換電路。在MAX+PLUSⅡ軟件平臺上，進行了編譯和波形仿真。綜合后下載到復雜可編程邏輯器件EPM7128SLC84-15中，測試結果表明，調制電路能正確選相，解調電路輸出數據與QDPSK調制輸入數據完全一致，達到了預期的設計要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
上傳時間： 2013-10-28
上傳用戶：jyycc
