dvbsnoop is a DVB/MPEG stream analyzer program. The program can be used to sniff, monitor, debug, dump or view DVB/MPEG/DSM-CC/MHP stream information (digital television or data broadcasts) sent via satellite, cable or terrestrial.
標簽： program dvbsnoop analyzer monitor
上傳時間： 2013-12-14
上傳用戶：zhangyi99104144
This application report introduces and describes an MP3 /AAC audio player for use with the TMS320C54x(TM) digital signal processor (DSP) devices. This audio player is based on Reference Framework Level 3 (RF3). Reference Framework for eXpressDSP(TM) Software is a start-ware for developing applications that use DSP/BIOS(TM) and the TMS320(TM) DSP AlgorithmStandard.
標簽： application introduces describes report
上傳時間： 2014-05-25
上傳用戶：x4587
人工智能中模糊邏輯算法 FuzzyLib 2.0 is a comprehensive C++ Fuzzy Logic library for constructing fuzzy logic systems with multi-controller support. It supports all commonly used shape functions and hedges, with full support for the various types of Aggregation, Correlation, Alphacut, Composition, Defuzzification methods. The latest version of the C++ Fuzzy Logic Class Library contains all the C++ source code and comes complete with a usage example for building a multi-controllers fuzzy logic model.
標簽： comprehensive constructing FuzzyLib library
上傳時間： 2013-12-17
上傳用戶：dbs012280
Welcome to PMOS. PMOS is a set of modules, mostly written in Modula-2, to support multitasking. PMOS was designed primarily with real-time applications in mind. It is not an operating system in the conventional sense rather, it is a collection of modules which you can import into your own programs, and which in particular allow you to write multi-threaded programs.
標簽： PMOS multitasking Welcome modules
上傳時間： 2015-07-10
上傳用戶：windwolf2000
一個Jtag調試仿真程序，兼容Multi-ICE，這是源代碼，很難找到的。特別推薦
上傳時間： 2013-12-12
上傳用戶：釣鰲牧馬
R+樹的c實現源碼，對應文章T. K. Sellis, N. Roussopoulos, C. Faloutsos: The R+-Tree: A Dynamic Index for Multi-Dimensional Objects.
上傳時間： 2014-05-25
上傳用戶：sunjet
硬件設計指南(PDF格式)，主要包括：Low Voltage Interfaces；Grounding in Mixed Signal Systems；Digital Isolation Techniques； Power Supply Noise Reduction and Filtering； Dealing with High Speed Logic
上傳時間： 2015-08-31
上傳用戶：阿四AIR
Verilog and VHDL狀態機設計，英文pdf格式 State machine design techniques for Verilog and VHDL Abstract : Designing a synchronous finite state Another way of organizing a state machine (FSM) is a common task for a digital logic only one logic block as shown in engineer. This paper will discuss a variety of issues regarding FSM design using Synopsys Design Compiler . Verilog and VHDL coding styles will be 2.0 Basic HDL coding presented. Different methodologies will be compared using real-world examples.
上傳時間： 2013-12-19
上傳用戶：change0329
I believe that technology has the capacity to fundamentally improve people’s lives, and improve the world in which we live.We are now two years into what my company have called the ‘Digital Decade’.We think that by 2010 a combination of hardware and software innovation with broader social trends will change the way computing fits into our society. Mobile technology is a central part of this vision.
標簽： improve fundamentally technology the
上傳時間： 2014-01-19
上傳用戶：kristycreasy
The function conload takes a dataset and a model (PCA, PLS, PARAFAC etc.) and calculates congruence loadings which is the extension of correlation loadings to uncentered and multi-way models
標簽： calculates congruence and function
上傳時間： 2014-01-08
上傳用戶：sz_hjbf
