// -*- Mode: Verilog -*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISHBONE Master // Supported cycles: MASTER, READ/WRITE // MASTER, BLOCK READ/WRITE // MASTER, RMW // Data port, size: 8, 16, 32-bit // Data port, granularity 8-bit // Data port, Max. operand size 32-bit // Data transfer ordering: little endian // Data transfer sequencing: undefined
資源簡(jiǎn)介:// -*- Mode: Verilog -*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : ...
上傳時(shí)間: 2014-07-11
上傳用戶(hù):zhanditian
資源簡(jiǎn)介:Filename: main.c * Description: A simple test program for the CRC implementations. * Notes: To test a different CRC standard, modify crc.h. * * * Copyright (c) 2000 by Michael Barr. This software is placed into * the public domain and may b...
上傳時(shí)間: 2015-02-02
上傳用戶(hù):leehom61
資源簡(jiǎn)介:IIR code. IEEE STD 1364-1995 Verilog file: iir_par.v.
上傳時(shí)間: 2013-12-23
上傳用戶(hù):xiaoxiang
資源簡(jiǎn)介:本文利用Verilog HDL 語(yǔ)言自頂向下的設(shè)計(jì)方法設(shè)計(jì)多功能數(shù)字鐘,突出了其作為硬件描述語(yǔ)言的良好的可讀性、可移植性和易理解等優(yōu)點(diǎn),并通過(guò)Altera QuartusⅡ 4.1 和ModelSim SE 6.0 完成綜合、仿真。此程序通過(guò)下載到FPGA 芯片后,可應(yīng)用于實(shí)際的數(shù)字鐘顯示中...
上傳時(shí)間: 2013-11-10
上傳用戶(hù):hz07104032
資源簡(jiǎn)介:是一個(gè)dsp程序,F(xiàn)ilename: ex10.asm * * Description: 濾波器實(shí)驗(yàn) * * Copyright(C) SanZhi Electronic, Author Zpin
上傳時(shí)間: 2015-06-04
上傳用戶(hù):royzhangsz
資源簡(jiǎn)介:·IEEE Std 1364-2001 Standard Verilog hardware Description language
上傳時(shí)間: 2013-06-20
上傳用戶(hù):蟲(chóng)蟲(chóng)蟲(chóng)蟲(chóng)蟲(chóng)蟲(chóng)
資源簡(jiǎn)介:為Filename 所指定的文件名按mode 模式創(chuàng)建一個(gè)FILE結(jié)構(gòu)數(shù)據(jù)區(qū),并將該數(shù)據(jù)區(qū)的首地址賦值給FILE類(lèi)型的指針變量fp.
上傳時(shí)間: 2013-12-09
上傳用戶(hù):時(shí)代電子小智
資源簡(jiǎn)介:Arbiter.v verilog實(shí)現(xiàn) 三路請(qǐng)求,使用循環(huán)策略的仲裁器 含有看門(mén)狗電路
上傳時(shí)間: 2013-12-10
上傳用戶(hù):qlpqlq
資源簡(jiǎn)介:This Verilog HDL Description implements a UART.
上傳時(shí)間: 2013-12-17
上傳用戶(hù):wff
資源簡(jiǎn)介:-- WISHBONE revB2 compiant I2C master core -- -- author: Richard Herveille -- rev. 0.1 based on simple_i2c -- rev. 0.2 april 27th 2001, fixed incomplete sensitivity list on assign_dato process (thanks to Matt Oseman) -- rev. 0.3 may 4t...
上傳時(shí)間: 2014-01-18
上傳用戶(hù):tzl1975
資源簡(jiǎn)介:verilog ADPLL file with testbench.v
上傳時(shí)間: 2015-07-09
上傳用戶(hù):cx111111
資源簡(jiǎn)介:master spi的源代碼(verilog),包括文檔,測(cè)試程序
上傳時(shí)間: 2014-01-13
上傳用戶(hù):拔絲土豆
資源簡(jiǎn)介:Filename: hal.h Target: cc2430 Author: EFU/ KJA Revised: 16/12-2005 Revision: 1.0 Description: Hardware Abstraction Layer - Utility Library for CC2430, CC2431, CC1110 and CC2510.
上傳時(shí)間: 2013-11-26
上傳用戶(hù):lanhuaying
資源簡(jiǎn)介:AT89S8252, AT89S53 SPI Program, This program shows how to configure and use the SPI in master mode for the following microcontrollers: ATMEL AT89S53 ATMEL AT89S8252
上傳時(shí)間: 2015-09-26
上傳用戶(hù):xlcky
資源簡(jiǎn)介:用verilog實(shí)現(xiàn)rs232通信async_transmitter.v
上傳時(shí)間: 2013-12-17
上傳用戶(hù):咔樂(lè)塢
資源簡(jiǎn)介:WISHBONE revB2 compiant I2C master core
上傳時(shí)間: 2015-10-05
上傳用戶(hù):2467478207
資源簡(jiǎn)介:一個(gè)好用的I2C接口master的verilog程序。
上傳時(shí)間: 2013-12-31
上傳用戶(hù):66666
資源簡(jiǎn)介:Accessing Atmel AT45Dxxx dataflash on STK500 .Sets up the HW SPI in Master mode
上傳時(shí)間: 2016-03-26
上傳用戶(hù):LIKE
資源簡(jiǎn)介:This example provides a Description of how to set a communication with the bxCAN in loopback mode: - transmit and receive a standard data frame by polling at 100Kbit/S - transmit and receive an extended data frame with interrupt at 500Kb...
上傳時(shí)間: 2016-04-24
上傳用戶(hù):frank1234
資源簡(jiǎn)介:This Verilog HDL Description implements a UART Version 1.1 : Original Creation 2.1 : added comments
上傳時(shí)間: 2016-05-27
上傳用戶(hù):1109003457
資源簡(jiǎn)介:數(shù)字計(jì)算機(jī)的設(shè)計(jì)coric,利用 verilog實(shí)現(xiàn),格式為.v格式.詳細(xì)見(jiàn)文件注釋
上傳時(shí)間: 2013-12-20
上傳用戶(hù):dongqiangqiang
資源簡(jiǎn)介:fifo.v verilog實(shí)現(xiàn)的先進(jìn)先出存儲(chǔ)器
上傳時(shí)間: 2016-08-25
上傳用戶(hù):GHF
資源簡(jiǎn)介:本程序包含:EEPROM的功能模型(eeprom.v)、讀/寫(xiě)EEPROM的verilog HDL 行為模塊(eeprom_wr.v)、信號(hào)產(chǎn)生模塊(signal.v)和頂層模塊(top.v) ,這樣可以有一個(gè)完整的EEPROM的控制模塊和測(cè)試文件,本文件通過(guò)測(cè)試。
上傳時(shí)間: 2017-01-22
上傳用戶(hù):lanjisu111
資源簡(jiǎn)介:用verilog HDL實(shí)現(xiàn)I2C Master Controller 的設(shè)計(jì),包括主程序設(shè)計(jì)和測(cè)試程序設(shè)計(jì)
上傳時(shí)間: 2014-01-04
上傳用戶(hù):tonyshao
資源簡(jiǎn)介:wishbone i2c master vhdl code
上傳時(shí)間: 2017-02-17
上傳用戶(hù):sunjet
資源簡(jiǎn)介:What is Verilog? ➥ Verilog HDL is a Hardware Description Language (HDL) ➥ Verilog HDL allows describe designs at a high level of abstraction as well as the lower implementation levels ➥ Primary use of HDLs is the simul...
上傳時(shí)間: 2017-02-18
上傳用戶(hù):
資源簡(jiǎn)介:SPI總線(xiàn)Master的verilog代碼
上傳時(shí)間: 2017-02-26
上傳用戶(hù):fredguo
資源簡(jiǎn)介:SPI master的verilog代碼
上傳時(shí)間: 2017-02-26
上傳用戶(hù):chenjjer
資源簡(jiǎn)介:i2c IP核 i2c.master i2c.mater.v
上傳時(shí)間: 2013-12-05
上傳用戶(hù):moerwang
資源簡(jiǎn)介:APB master verilog code
上傳時(shí)間: 2013-12-06
上傳用戶(hù):zhengzg