This Verilog HDL description implements a UART Version 1.1 : Original Creation 2.1 : added comments
資源簡(jiǎn)介:This Verilog HDL description implements a UART Version 1.1 : Original Creation 2.1 : added comments
上傳時(shí)間: 2016-05-27
上傳用戶:1109003457
資源簡(jiǎn)介:This Verilog HDL description implements a UART.
上傳時(shí)間: 2013-12-17
上傳用戶:wff
資源簡(jiǎn)介:Verilog HDL: Magnitude For a vector (a,b), the magnitude representation is the following: A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC ...
上傳時(shí)間: 2013-12-24
上傳用戶:金宜
資源簡(jiǎn)介:This document is a simplified version of the Original. This version is not required to be treated as confidential and Non Disclosure Agreement with neither the 3C LLC nor the SDA is required. Reproduction in whole or in part is prohibited...
上傳時(shí)間: 2014-12-08
上傳用戶:zhangyi99104144
資源簡(jiǎn)介:this is a verilog hdl language referance book , tell you the basic useage of this language.
上傳時(shí)間: 2016-02-06
上傳用戶:日光微瀾
資源簡(jiǎn)介:this a Uart source code using Verilog.
上傳時(shí)間: 2016-05-19
上傳用戶:zsjzc
資源簡(jiǎn)介:this a book about the verilog-hdl design and circuit simulation and synthesize example
上傳時(shí)間: 2016-11-03
上傳用戶:GavinNeko
資源簡(jiǎn)介:What is Verilog? ➥ Verilog HDL is a Hardware description Language (HDL) ➥ Verilog HDL allows describe designs at a high level of abstraction as well as the lower implementation levels ➥ Primary use of HDLs is the simul...
上傳時(shí)間: 2017-02-18
上傳用戶:
資源簡(jiǎn)介:·詳細(xì)說(shuō)明:正式出版物《Verilog HDL 硬件描述語(yǔ)言》一書的精美 PDF 電子版。- Official publication Verilog HDL Hardware description Language a book fine PDF electron version.目????? 錄譯者序前言第1章?? 簡(jiǎn)介&n
上傳時(shí)間: 2013-07-02
上傳用戶:6404552
資源簡(jiǎn)介:本文利用Verilog HDL 語(yǔ)言自頂向下的設(shè)計(jì)方法設(shè)計(jì)多功能數(shù)字鐘,突出了其作為硬件描述語(yǔ)言的良好的可讀性、可移植性和易理解等優(yōu)點(diǎn),并通過Altera QuartusⅡ 4.1 和ModelSim SE 6.0 完成綜合、仿真。此程序通過下載到FPGA 芯片后,可應(yīng)用于實(shí)際的數(shù)字鐘顯示中...
上傳時(shí)間: 2013-11-10
上傳用戶:hz07104032
資源簡(jiǎn)介:·Verilog?HDL:?A?Guide?to?Digital?Design?and??
上傳時(shí)間: 2013-04-24
上傳用戶:誰(shuí)偷了我的麥兜
資源簡(jiǎn)介:·Verilog HDL Synthesis, A Practical Primer
上傳時(shí)間: 2013-04-24
上傳用戶:muhongqing
資源簡(jiǎn)介:This package is a special version of the Reed-Solomon package
上傳時(shí)間: 2014-12-03
上傳用戶:lwwhust
資源簡(jiǎn)介:This driver implements a COM port interface for USB Point-of-Sale devices
上傳時(shí)間: 2013-12-22
上傳用戶:希醬大魔王
資源簡(jiǎn)介:Lattice公司的A Verilog HDL Test Bench Primer應(yīng)用手冊(cè)
上傳時(shí)間: 2015-04-25
上傳用戶:宋桃子
資源簡(jiǎn)介:硬件uart源程序verilog HDL,即相關(guān)文檔
上傳時(shí)間: 2015-04-25
上傳用戶:pompey
資源簡(jiǎn)介:This example implements a gameport translator on the PIC16C765. The firmware translates a gaming device plugged into the gameport to a USB gaming device. The firmware is set up to translate the DexxaTM eight-button gamepad. Changes to...
上傳時(shí)間: 2015-04-26
上傳用戶:yyq123456789
資源簡(jiǎn)介:UART verilog hdl 實(shí)現(xiàn)
上傳時(shí)間: 2014-01-11
上傳用戶:PresidentHuang
資源簡(jiǎn)介:This package implements a Kalman filter as described in the paper "A Statistical Algorithm for Estimating Speed from Single Loop Volume and Occupancy Measurements" by D. J. Dailey.
上傳時(shí)間: 2013-12-12
上傳用戶:cc1915
資源簡(jiǎn)介:FPGA/CPLD應(yīng)用,uart的Verilog HDL原碼
上傳時(shí)間: 2013-12-28
上傳用戶:lizhizheng88
資源簡(jiǎn)介:是一本好書,verilog HDL,a guide to digital design and synthesis
上傳時(shí)間: 2015-07-14
上傳用戶:熊少鋒
資源簡(jiǎn)介:JK Proxy Project - Version 0.1 ------------------------------ This was going to be a proxy server bu I stopped developing this program (maybe I will go on coding on this application again some time). The email part with spam filteri...
上傳時(shí)間: 2014-08-10
上傳用戶:coeus
資源簡(jiǎn)介:Verilog HDL Synthesis, A Practical Primer 學(xué)習(xí)Verilog HDL一本很不錯(cuò)的英文書,比較透徹
上傳時(shí)間: 2016-01-19
上傳用戶:hongmo
資源簡(jiǎn)介:占用資源少的verilog HDL uart接口;采用固定波特率115200,可以修改程序中的分頻來(lái)修改波特率,模式為1個(gè)啟始位,8位數(shù)據(jù)位,1個(gè)停止位;帶1字節(jié)緩存;當(dāng)緩存空時(shí)輸出空信號(hào)
上傳時(shí)間: 2013-12-28
上傳用戶:kikye
資源簡(jiǎn)介:This document contains a description of the CAN Reference Model. This document is part of a set of documents that standardize the CAN Application Layer for Industrial Applications.
上傳時(shí)間: 2016-02-08
上傳用戶:yoleeson
資源簡(jiǎn)介:實(shí)現(xiàn)簡(jiǎn)單的UART功能,在QUARTUS4.0下編譯通過,采用VERILOG HDL編寫.
上傳時(shí)間: 2013-12-18
上傳用戶:hfmm633
資源簡(jiǎn)介:this is a vhdl version of MiniUART implementation
上傳時(shí)間: 2014-09-05
上傳用戶:1079836864
資源簡(jiǎn)介:UART轉(zhuǎn)I2C的Verilog HDL代碼,由北京郵電大學(xué)《VerilogHDL設(shè)計(jì)與EDA技術(shù)基礎(chǔ)》教師編寫
上傳時(shí)間: 2014-08-03
上傳用戶:zhuoying119
資源簡(jiǎn)介:uart串口通信程序 用VERILOG HDL 編寫 可以有效應(yīng)用于FPGA上
上傳時(shí)間: 2014-01-04
上傳用戶:頂?shù)弥?/p>
資源簡(jiǎn)介:UART實(shí)驗(yàn)Verilog HDL代碼,用于FPGA
上傳時(shí)間: 2014-01-09
上傳用戶:linlin