What is Verilog? ➥ Verilog HDL is a Hardware Description Language (HDL) ➥ Verilog HDL allows describe designs at a high level of abstraction as well as the lower implementation levels ➥ Primary use of HDLs is the simulation of designs ➥ Verilog is a discrete event time simulator What is VeriWell? ➥ VeriWell is a comprehensive implementation of Verilog HDL
資源簡(jiǎn)介:What is Verilog? ➥ Verilog HDL is a Hardware Description Language (HDL) ➥ Verilog HDL allows describe designs at a high level of abstraction as well as the lower implementation levels ➥ Primary use of HDLs is the simul...
上傳時(shí)間: 2017-02-18
上傳用戶:
資源簡(jiǎn)介:·IEEE Std 1364-2001 Standard Verilog hardware Description language
上傳時(shí)間: 2013-06-20
上傳用戶:蟲蟲蟲蟲蟲蟲
資源簡(jiǎn)介:The Verilog Hardware Description Language, 5th Ed
上傳時(shí)間: 2018-04-15
上傳用戶:MagicJ
資源簡(jiǎn)介:As the Hardware Description Language (HDL) enhancement activities have increased over the past year, so too has the complexity in determining which language(s) are the best tools for designers and organizations to continue using or to adopt...
上傳時(shí)間: 2015-12-15
上傳用戶:sunjet
資源簡(jiǎn)介:As the Hardware Description Language (HDL) enhancement activities have increased over the past year, so too has the complexity in determining which language(s) are the best tools for designers and organizations to continue using or to adopt...
上傳時(shí)間: 2015-12-15
上傳用戶:SimonQQ
資源簡(jiǎn)介:本文利用Verilog HDL 語言自頂向下的設(shè)計(jì)方法設(shè)計(jì)多功能數(shù)字鐘,突出了其作為硬件描述語言的良好的可讀性、可移植性和易理解等優(yōu)點(diǎn),并通過Altera QuartusⅡ 4.1 和ModelSim SE 6.0 完成綜合、仿真。此程序通過下載到FPGA 芯片后,可應(yīng)用于實(shí)際的數(shù)字鐘顯示中...
上傳時(shí)間: 2013-11-10
上傳用戶:hz07104032
資源簡(jiǎn)介:硬件描述語言(英文: Hardware Description Language ,簡(jiǎn)稱: HDL )是電子系統(tǒng)硬件行為描述、結(jié)構(gòu)描述、數(shù)據(jù)流描述的語言。利用這種語言,數(shù)字電路系統(tǒng)的設(shè)計(jì)可以從頂層到底層(從抽象到具體)逐層描述自己的設(shè)計(jì)思想,用一系列分層次的模塊來表示極其復(fù)雜...
上傳時(shí)間: 2021-12-24
上傳用戶:zhanglei193
資源簡(jiǎn)介:·Verilog HDL Synthesis, A Practical Primer
上傳時(shí)間: 2013-04-24
上傳用戶:muhongqing
資源簡(jiǎn)介:What I did with this class is to automatize (not MS s automation) several processes to do a search in a MS Sql Server database, and show the results, retaining the data on an internal structure
上傳時(shí)間: 2015-10-11
上傳用戶:manlian
資源簡(jiǎn)介:Verilog HDL Synthesis, A Practical Primer 學(xué)習(xí)Verilog HDL一本很不錯(cuò)的英文書,比較透徹
上傳時(shí)間: 2016-01-19
上傳用戶:hongmo
資源簡(jiǎn)介:(2003 prentice-hall)Verilog HDL:a guide to digital design and synthesis(2nd edition).rar
上傳時(shí)間: 2014-01-17
上傳用戶:teddysha
資源簡(jiǎn)介:·詳細(xì)說明:正式出版物《Verilog HDL 硬件描述語言》一書的精美 PDF 電子版。- Official publication Verilog HDL Hardware Description Language a book fine PDF electron version.目????? 錄譯者序前言第1章?? 簡(jiǎn)介&n
上傳時(shí)間: 2013-07-02
上傳用戶:6404552
資源簡(jiǎn)介:THIS is really two books in one: a tutorial and a reference manual for JDBC, the application programming interface that makes it possible for programmers to access databases from Java. The goal is to be useful to a wide range of readers, fr...
上傳時(shí)間: 2015-08-04
上傳用戶:zhengzg
資源簡(jiǎn)介:megahal is the conversation simulators conversing with a user in natural language. The program will exploit the fact that human beings tend to read much more meaning into what is said than is actually there MegaHAL differs from conversatio...
上傳時(shí)間: 2015-10-09
上傳用戶:lnnn30
資源簡(jiǎn)介:The use of hardware Description languages (HDLs) is becoming increasingly common for designing and verifying FPGA designs. Behavior level Description not only increases design productivity, but also provides unique advantages for design ...
上傳時(shí)間: 2014-01-08
上傳用戶:小草123
資源簡(jiǎn)介:·SystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog HDL). These extensions address two major aspects of HDL-based design. First, modeling ver
上傳時(shí)間: 2013-07-14
上傳用戶:ainimao
資源簡(jiǎn)介:Massively Multiplayer Space Trading and Combat game. This is an online strategy game, not a 3D space sim. Incorporating ideas from games such as Stars!, SE3, MOO, Tradewars, MUD/MOOs, Dune II, SimCity.
上傳時(shí)間: 2015-01-10
上傳用戶:caiiicc
資源簡(jiǎn)介:The CC1000 RF transceiver is very easy to interface with a microcontroller. The chip is configured using a three-wire bus, comprising of PCLK, PDATA and PALE signals.
上傳時(shí)間: 2014-01-04
上傳用戶:c12228
資源簡(jiǎn)介:The storage management system "is uses VISAUL the FOXPRO development a database management system.
上傳時(shí)間: 2013-12-22
上傳用戶:klin3139
資源簡(jiǎn)介:This is simple sample program to test a File System integrity
上傳時(shí)間: 2015-06-19
上傳用戶:gaojiao1999
資源簡(jiǎn)介:It is the framework of Registration of a PKI. It will retrive requests from a request queue and then process it
上傳時(shí)間: 2015-08-27
上傳用戶:chongcongying
資源簡(jiǎn)介:This is the machine-generated representation of a Handle Graphics object and its children. Note that handle values may change when these objects are re-created. This may cause problems with any callbacks written to depend on the value o...
上傳時(shí)間: 2013-12-18
上傳用戶:miaochun888
資源簡(jiǎn)介:it is a 8 bit multiplication vHDL program.sorry ,my english is poor ,but my programmor is used.
上傳時(shí)間: 2014-07-18
上傳用戶:英雄
資源簡(jiǎn)介:SAM9261 BasicMMU Example code with ADS1.2 (163 kB) The goal of this project is to show how to use a PC100 SDRAM and the MMU to perform a rating with a 100MHz Bus Clock. The rating is based on Dhrystone 2.1. It shows the rate when I+D Caches...
上傳時(shí)間: 2013-12-28
上傳用戶:zhanditian
資源簡(jiǎn)介:As all of you know, MATLAB is a powerful engineering language. Because of some limitation, some tasks take very long time to proceed. Also MATLAB is an interpreter not a compiler. For this reason, executing a MATLAB program (m file) is time...
上傳時(shí)間: 2013-12-06
上傳用戶:huql11633
資源簡(jiǎn)介:This handbook is intended for anyone who wants a comprehensive survey of Fortran 90, including those familiar with programming language concepts but unfamiliar with Fortran. Experienced Fortran 77 programmers will be able to use this vol...
上傳時(shí)間: 2013-11-27
上傳用戶:lvzhr
資源簡(jiǎn)介:Design and Test_Verilog HDL——EDA先鋒工作室《設(shè)計(jì)與驗(yàn)證—Verilog HDL》配書源代碼,很多使用的實(shí)例,并有說明,是學(xué)習(xí)Verilog 不可多得的好資料。
上傳時(shí)間: 2016-02-18
上傳用戶:youlongjian0
資源簡(jiǎn)介:TxQuery is an SQL engine implemented in a TDataSet descendant component, that can parse SQL syntax, and that will use that syntax to query to another.
上傳時(shí)間: 2014-01-01
上傳用戶:LouieWu
資源簡(jiǎn)介:The aim of this book is to provide the reader with a thorough grounding in the General Packet Radio Service – GPRS.The introduction contains a basic review of GSM to ensure that the reader is clear on the main aspects of circuit switched ...
上傳時(shí)間: 2016-03-30
上傳用戶:康郎
資源簡(jiǎn)介:check if there is char over than 72 in a line.
上傳時(shí)間: 2014-11-30
上傳用戶: