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Make and answer phone calls Detect tone and pulse digit from the phone line Capture Caller ID Support blind transfer, single-step transfer/conference, consultation transfer/conference, hold, unhold. Control of the local phone handset, microphone and speaker of the modem Send and receive faxes Play and record on the phone line or sound card Play music in background mode Silence detection VU Meter Wave sound editor that allows your end-users to edit their own sound files. Voice recognition and voice synThesis. Full control over the serial port device ZModem file transfer utility File compression and encryption utility
上傳時間： 2013-11-30
上傳用戶：水中浮云
This paper presents the key circuits of a 1MHz bandwidth, 750kb/s GMSK transmitter. The fractional-N synthesizer forming the basis of the transmitter uses a combined phasefrequency detector (PFD) and digital-to-analog converter (DAC) circuit element to obtain >28dB high frequency noise reduction when compared to classicalfrequency synThesis.
標簽： fractional-N transmitter bandwidth circuits
上傳時間： 2016-04-14
上傳用戶：er1219
This file contains a selection of VHDL source files which serve to illustrate the diversity and power of the language when used to describe various types of hardware. The examp terms of basic logic gates, to more complex systems, such as a behavioural model of a microprocessor and associated memory. All of the examples can be simulated using any synThesised using current synThesis tools.
標簽： illustrate diversity selection contains
上傳時間： 2016-06-06
上傳用戶：yimoney
FIR濾波器的C++實現 Below are program source listings for FIR.h and FIR.cpp, the header file and class file for implementing arbitrary causal FIR filters in the synThesis Tool Kit (STK) framework
上傳時間： 2013-12-11
上傳用戶：heart520beat
With the advent of multimedia, digital signal processing (DSP) of sound has emerged from the shadow of bandwidth-limited speech processing. Today, the main appli- cations of audio DSP are high quality audio coding and the digital generation and manipulation of music signals. They share common research topics including percep- tual measurement techniques and analysis/synThesis methods. Smaller but nonetheless very important topics are hearing aids using signal processing technology and hardware architectures for digital signal processing of audio. In all these areas the last decade has seen a significant amount of application oriented research.
標簽： multimedia processing the digital
上傳時間： 2014-01-23
上傳用戶：xwd2010
DDR SDRAM控制器的VHDL源代碼，含詳細設計文檔。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency synThesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.
上傳時間： 2014-11-01
上傳用戶：l254587896
ECE345, Visual-to-Audio Electronic Travel Aid Code for TM320C54x (v2a.asm) download This project involves the design and implementation of a audio synThesis device that converts moving images into audio signals. The system is built on a TM320C54x DSP with interface to an IMAQ camera module via the serial port on a PC. Brief description: A LabVIEW VI acquires an image from the IMAQ camera module. It quantizes the image into a 5x5, 3-bit image, and sends the data to the TM320C54x DSP via a serial port. The TM320C54x DSP constructs a 64-tap FIR by combining a series of 64-tap head related transfer functions (HRTF) according to the incoming data, and then filters an input audio signal with this FIR filter, in effect creating a correspondence between the filtered signal and the original image.
標簽： Visual-to-Audio Electronic download project
上傳時間： 2017-02-01
上傳用戶：笨小孩
8051單片機源碼verilog版本 包括rtl， testbench， synThesis
上傳時間： 2014-01-14
上傳用戶：yuanyuan123
1. Learn the basic constructs of VHDL 2. Learn the modeling structure of VHDL 3. Understand the design environments – Simulation – synThesis
標簽： the Learn VHDL Understand
上傳時間： 2017-02-18
上傳用戶：love_stanford
The xapp851.zip archive includes the following subdirectories. The specific contents of each subdirectory below: \rtl - HDL design files \sim - simulation files \synth - synThesis related files \par - Place/Route related files
標簽： subdirectories The following includes
上傳時間： 2014-01-25
上傳用戶：lepoke
