Electronic design automation (EDA) company providing logic synThesis and analysis tools for FPGA and ASIC designers.
標(biāo)簽： Electronic automation and providing
上傳時(shí)間： 2014-01-10
上傳用戶：四只眼
32bits FIFO with synchronizer. pass the synThesis using Synopsys tools
標(biāo)簽： synchronizer synThesis Synopsys using
上傳時(shí)間： 2015-07-13
上傳用戶：zyt
是一本好書(shū),verilog HDL,a guide to digital design and synThesis
標(biāo)簽： synThesis verilog digital design
上傳時(shí)間： 2015-07-14
上傳用戶：熊少鋒
Artifical Intelligence A new synThesis (中文版) PDF格式
標(biāo)簽： Intelligence Artifical synThesis new
上傳時(shí)間： 2014-01-07
上傳用戶：ryb
The MATLAB coding style, project options and synThesis directives can have a significant effect on the final results. Knowledge about how a particular algorithm should be implemented in hardware can be reflected in the MATLAB code to improve the results. In doing so, the MATLAB loses a bit of its abstraction but the lower-level MATLAB will infer the desired architecture into the device.
標(biāo)簽： significant directives synThesis project
上傳時(shí)間： 2013-12-03
上傳用戶：13517191407
Efficient MSP430 Code synThesis for an FIR Filter
標(biāo)簽： Efficient synThesis Filter Code
上傳時(shí)間： 2014-01-09
上傳用戶：aa54
Verilog HDL synThesis, A Practical Primer 學(xué)習(xí)Verilog HDL一本很不錯(cuò)的英文書(shū)，比較透徹
標(biāo)簽： Verilog HDL synThesis Practical
上傳時(shí)間： 2016-01-19
上傳用戶：hongmo
直接數(shù)字頻率合成（Direct Digital Fraquency synThesis,即DDFS，一般簡(jiǎn)稱DDS）是從相位概念出發(fā)直接合成所需要波形的一種新的頻率合成技術(shù)。
標(biāo)簽： Fraquency synThesis Digital Direct
上傳時(shí)間： 2016-01-28
上傳用戶：aa54
AccelDSP synThesis Tool Floating-Point to Fixed-Point Conversion of MATLAB Algorithms Targeting FPGAs
標(biāo)簽： Floating-Point Fixed-Point Conversion Algorithms
上傳時(shí)間： 2014-01-14
上傳用戶：wangzhen1990
A Guide To Digital Design And synThesis - 2Nd Ed 2003A Guide To Digital Design And synThesis - 2Nd Ed 2003
標(biāo)簽： synThesis Digital Design Guide
上傳時(shí)間： 2016-03-04
上傳用戶：洛木卓
蟲(chóng)蟲(chóng)下載站版權(quán)所有 京ICP備2021023401號(hào)-1
