-- Booth Multiplier -- This file contains all the entity-architectures for a complete -- k-bit x k-bit Booth multiplier. -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synThesis check -- download from: www.fpga.com.cn & www.pld.com.cn
標簽： entity-architectures Multiplier contains complete
上傳時間： 2015-07-02
上傳用戶：2467478207
波形發生器，帶TESTBENCH， 多平臺 -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synThesis check -- download from: www.fpga.com.cn & www.pld.com.cn
標簽： 波形發生器
上傳時間： 2014-01-20
上傳用戶：familiarsmile
1)Learn more about the capabilities in Quartus: 2)Learn to use different design entry techniques 2)Design entry methods available within Quartus Text editor,Block diagram/schematic file editor, Quartus interface with design entry/synThesis tools from Exemplar, Synopsys, Synplicity and Viewlogic
標簽： Learn capabilities techniques different
上傳時間： 2014-01-18
上傳用戶：yxgi5
關于FPGA流水線設計的論文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. synThesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
標簽： investigates implementing pipelines circuits
上傳時間： 2015-07-26
上傳用戶：CHINA526
Often it is necessary to add some logical control to a MATLAB algorithm to allow the generated hardware to function correctly in the overall system. This lab exercise will explore how hardware control can be added to a MATLAB algorithm and synthesized using AccelDSP synThesis.
標簽： algorithm generated necessary to
上傳時間： 2014-01-25
上傳用戶：yimoney
Demonstrates 1-D FDTD initial state formation. Please edit the FLAGS for demonstration of different cases. BASED ON "1-D Digital Waveguide Modeling for Improved Sound synThesis".
標簽： demonstration Demonstrates formation different
上傳時間： 2014-07-13
上傳用戶：WMC_geophy
-- Booth Multiplier -- This file contains all the entity-architectures for a complete -- k-bit x k-bit Booth multiplier. -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synThesis check
標簽： entity-architectures Multiplier contains complete
上傳時間： 2014-01-22
上傳用戶：lijianyu172
vTools is a toolbox for Matlab 5.3 developed within the Department of Electrical Systems and Automation (DSEA) of the University of Pisa (Italy) with the aim to offering to the Matlab users (especially control engineers and control engineering students) a completely graphical toolbox for linear system analysis and robust control synThesis
標簽： Department Electrical developed Systems
上傳時間： 2013-12-25
上傳用戶：tyler
The VHDL Golden Reference Guide is a compact quick reference guide to the VHDL language, its syntax, semantics, synThesis and application to hardware design.
標簽： VHDL Reference reference language
上傳時間： 2014-12-21
上傳用戶：chenbhdt
The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around a common on-chip bus, and use a coherent method for simulation and synThesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources.
標簽： system-on-chip integrated designed reusable
上傳時間： 2015-11-17
上傳用戶：D&L37
