利用verlilog hdl語(yǔ)言編程，完成了8051內(nèi)核，非常值得學(xué)習(xí)硬件描述語(yǔ)言的人看看！
標(biāo)簽： verlilog hdl 語(yǔ)言編程
上傳時(shí)間： 2015-12-10
上傳用戶：erkuizhang
該代碼中有不少關(guān)于學(xué)習(xí)verilog HDL的例子,對(duì)初學(xué)者有幫助
標(biāo)簽： verilog HDL 代碼 初學(xué)者
上傳時(shí)間： 2013-12-19
上傳用戶：asdkin
Verilog HDL課件，有常見(jiàn)問(wèn)題說(shuō)明
上傳時(shí)間： 2013-12-21
上傳用戶：sdq_123
Verilog HDL的標(biāo)準(zhǔn)，比較詳細(xì)的語(yǔ)法說(shuō)明
標(biāo)簽： Verilog HDL 標(biāo)準(zhǔn)
上傳時(shí)間： 2015-12-15
上傳用戶：xsnjzljj
As the Hardware Description Language (HDL) enhancement activities have increased over the past year, so too has the complexity in determining which language(s) are the best tools for designers and organizations to continue using or to adopt. Many designers and organizations are contemplating whether they should switch from one HDL to another.
標(biāo)簽： Description enhancement activities the
上傳時(shí)間： 2015-12-15
上傳用戶：sunjet
Testbenches have become an integral part of the design process, enabling you to verify that your HDL model is sufficiently tested before implementing your design and helping you automate the design verification process. It is essential, therefore, that you have confidence your testbench is thoroughly exercising your design. Collecting code coverage statistics during simulation helps to ensure the quality and thoroughness of your tests.
標(biāo)簽： Testbenches enabling integral process
上傳時(shí)間： 2014-01-25
上傳用戶：ynzfm
As the Hardware Description Language (HDL) enhancement activities have increased over the past year, so too has the complexity in determining which language(s) are the best tools for designers and organizations to continue using or to adopt. Many designers and organizations are contemplating whether they should switch from one HDL to another.
標(biāo)簽： Description enhancement activities the
上傳時(shí)間： 2015-12-15
上傳用戶：SimonQQ
臺(tái)灣verilog hdl硬件描述性語(yǔ)言，適合有基礎(chǔ)的人
標(biāo)簽： verilog hdl 硬件 語(yǔ)言
上傳時(shí)間： 2014-01-09
上傳用戶：13681659100
采用Verilog HDL硬件語(yǔ)言設(shè)計(jì),實(shí)現(xiàn)基本的公用電話計(jì)費(fèi)功能,設(shè)計(jì)完整.
標(biāo)簽： Verilog HDL 硬件語(yǔ)言設(shè)計(jì) 電話
上傳時(shí)間： 2014-01-11
上傳用戶：tzl1975
】 本文主要討論了Modbus 通信協(xié)議的R TU 幀格式中常用的錯(cuò)誤校驗(yàn)方法,即循環(huán)冗余校驗(yàn)法( CRC) 。 提出了Modbus 協(xié)議反轉(zhuǎn)CRC 校驗(yàn)的方法,推導(dǎo)了反轉(zhuǎn)CRC 校驗(yàn)快速計(jì)算表格,并用C 語(yǔ)言實(shí)現(xiàn)了基于快速查 表算法的循環(huán)冗余校驗(yàn)程序。
標(biāo)簽： Modbus CRC TU 通信協(xié)議
上傳時(shí)間： 2015-12-16
上傳用戶：498732662
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