This program applies Message Digest MD5 Algorithm Developed by Maimouna Al-ammar 5th Year, Computer Engineering Department, University of Damascus Information and Network Security Material
標簽： Algorithm Developed Al-ammar Maimouna
上傳時間： 2017-08-10
上傳用戶：努力努力再努力
Imp java questions. very important for java interview for experienced professional more than 1 year
標簽： java professional experienced important
上傳時間： 2013-12-19
上傳用戶：894898248
本文簡單討論并總結了VHDL、Verilog，System verilog 這三中語言的各自特點和區別As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.
標簽： Verilog verilog System VHDL
上傳時間： 2013-10-16
上傳用戶：牛布牛
Each year Vishay releases thousands of new components that enable our customers to create new and superior end products. We recognize that offering unique component solutions helps improve the performance of next-generation devices, overcome technical barriers, and create new markets.
上傳時間： 2013-12-14
上傳用戶：ming529
Features: High efficiency, high reliability, low cost AC input range selected by switch 100% full load burn-in test Protections: Short circuit / Over load Fixed switching frequency at 25KHz Cooling by free air convection 1 year warranty Dimensions: 199*98*38mm (L*W*H)
標簽： Switchin Output Single SKS
上傳時間： 2013-10-30
上傳用戶：taa123456
SHUZIZHONG顯示電路 源程序如下： #include <reg51.h>#include <intrins.h> unsigned char data dis_digit; unsigned char code dis_code[]={ 0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7d,0x07,0x7f,0x6f,0x77,0x7c,0x39,0x5e,0x79,0x71};unsigned char data dis_buf[16];unsigned char data dis_index;char hour,min,sec,wang,year,mouth,day;unsigned char sec100;
上傳時間： 2013-11-24
上傳用戶：fdmpy
特點 精確度0.1%滿刻度 ±1位數 顯示范圍-19999-99999可任意規劃 可直接量測直流電流/直流電壓,無需另接輔助電源 尺寸小(24x48x50mm),穩定性高 分離式端子,配線容易 CE 認證 2.主要規格 輔助電源: None 精確度: 0.1% F.S. ±1 digit(1-100%F.S.) 輸入抗阻 : >100Mohm(<2V range) >2Mohm(<2Vrange) < 0.25VA(current ranges) < 1000Vrms(>54V ranges) 最大過載能力: < 150Vrms(<54V ranges)
上傳時間： 2013-10-08
上傳用戶：tiantwo
12864液晶時鐘顯示程序 LCD 地址變量 ;**************變量的定義***************** RS BIT P2.0 ;LCD數據/命令選擇端(H/L) RW BIT P2.1 ;LCD讀/寫選擇端(H/L) EP BIT P2.2 ;LCD使能控制 PSB EQU P2.3 RST EQU P2.5 PRE BIT P1.4 ;調整鍵(K1) ADJ BIT P1.5 ;調整鍵(K2) COMDAT EQU P0 LED EQU P0.3 YEAR DATA 18H ;年,月,日變量 MONTH DATA 19H DATE DATA 1AH WEEK DATA 1BH HOUR DATA 1CH ;時,分,秒,百分之一秒變量 MIN DATA 1DH SEC DATA 1EH SEC100 DATA 1FH STATE DATA 23H LEAP BIT STATE.1 ;是否閏年標志1--閏年，0--平年 KEY_S DATA 24H ;當前掃描鍵值 KEY_V DATA 25H ;上次掃描鍵值 DIS_BUF_U0 DATA 26H ;LCD第一排顯示緩沖區 DIS_BUF_U1 DATA 27H DIS_BUF_U2 DATA 28H DIS_BUF_U3 DATA 29H DIS_BUF_U4 DATA 2AH DIS_BUF_U5 DATA 2BH DIS_BUF_U6 DATA 2CH DIS_BUF_U7 DATA 2DH DIS_BUF_U8 DATA 2EH DIS_BUF_U9 DATA 2FH DIS_BUF_U10 DATA 30H DIS_BUF_U11 DATA 31H DIS_BUF_U12 DATA 32H DIS_BUF_U13 DATA 33H DIS_BUF_U14 DATA 34H DIS_BUF_U15 DATA 35H DIS_BUF_L0 DATA 36H ;LCD第三排顯示緩沖區 DIS_BUF_L1 DATA 37H DIS_BUF_L2 DATA 38H DIS_BUF_L3 DATA 39H DIS_BUF_L4 DATA 3AH DIS_BUF_L5 DATA 3BH DIS_BUF_L6 DATA 3CH DIS_BUF_L7 DATA 3DH DIS_BUF_L8 DATA 3EH DIS_BUF_L9 DATA 3FH DIS_BUF_L10 DATA 40H DIS_BUF_L11 DATA 41H DIS_BUF_L12 DATA 42H DIS_BUF_L13 DATA 43H DIS_BUF_L14 DATA 44H DIS_BUF_L15 DATA 45H FLAG DATA 46H ;1-年，2-月，3-日，4-時，5-分，6-秒，7-退出調整。 DIS_H DATA 47H DIS_M DATA 48H DIS_S DATA 49H
上傳時間： 2013-11-09
上傳用戶：xingisme
本文簡單討論并總結了VHDL、Verilog，System verilog 這三中語言的各自特點和區別As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.
標簽： Verilog verilog System VHDL
上傳時間： 2014-03-03
上傳用戶：zhtzht
The data plane of the reference design consists of a configurable multi-channel XBERT modulethat generates and checks high-speed serial data transmitted and received by the MGTs. Eachchannel in the XBERT module consists of two MGTs (MGTA and MGTB), which physicallyoccupy one MGT tile in the Virtex-4 FPGA. Each MGT has its own pattern checker, but bothMGTs in a channel share the same pattern generator. Each channel can load a differentpattern. The MGT serial rate depends on the reference clock frequency and the internal PMAdivider settings. The reference design can be scaled anywhere from one channel (two MGTs)to twelve channels (twenty-four MGTs).
上傳時間： 2013-12-25
上傳用戶：jkhjkh1982
