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  • 無線電干擾 Radio Susceptibility

      Abstract: Engineers often wish that radio susceptibility (RS) or radio immunity could be cured with an antibiotic, a vaccine, or someform of cure-all. Unfortunately, solving the RS problem is not that easy. Indeed, the laws of physics apply. In this article we discusssources of RS. We also offer tips and hints to protect systems, power supplies, printed circuit boards (PCBs), and electroniccomponents from radio frequency interference.

    標簽: Susceptibility Radio 無線電干擾

    上傳時間: 2014-12-30

    上傳用戶:旗魚旗魚

  • SMT生產(chǎn)線貼片機負荷均衡優(yōu)化

    摘要:采用表面組裝技術(surface mountt echnology,SMT)進行印制板級電子電路組裝是當代組裝技術發(fā)展的主流。典型的SMT生產(chǎn)線是由高速機和多功能機串聯(lián)而成,印制電路板(printed circuit board,PCB)上的元器件在貼片機之間的負荷均衡優(yōu)化問題是SMT生產(chǎn)調(diào)度的關鍵問題。以使貼片時間與更換吸嘴時間之和最大的工作臺生產(chǎn)時間最小化為目標構建了負荷均衡模型,開發(fā)了相應的遺傳算法,并進行了數(shù)值實驗與算法評價。與生產(chǎn)時間理論下界和現(xiàn)場機器自帶軟件調(diào)度方案的對比表明了模型及其算法的有效性。關鍵詞:印制電路板;表面組裝生產(chǎn)線;負荷分配;生產(chǎn)線優(yōu)化

    標簽: SMT 生產(chǎn)線 均衡 貼片機

    上傳時間: 2013-10-09

    上傳用戶:亞亞娟娟123

  • PCB Design Considerations and Guidelines for 0.4mm and 0.5mm WLPs

    Abstract: Using a wafer-level package (WLP) can reduce the overall size and cost of your solution.However when using a WLP IC, the printed circuit board (PCB) layout can become more complex and, ifnot carefully planned, result in an unreliable design. This article presents some PCB designconsiderations and general recommendations for choosing a 0.4mm- or 0.5mm-pitch WLP for yourapplication.

    標簽: Considerations Guidelines and Design

    上傳時間: 2013-11-09

    上傳用戶:ls530720646

  • 多層印制板設計基本要領

    【摘要】本文結合作者多年的印制板設計經(jīng)驗,著重印制板的電氣性能,從印制板穩(wěn)定性、可靠性方面,來討論多層印制板設計的基本要求。【關鍵詞】印制電路板;表面貼裝器件;高密度互連;通孔【Key words】printed Circuit Board;Surface Mounting Device;High Density Interface;Via一.概述印制板(PCB-printed Circuit Board)也叫印制電路板、印刷電路板。多層印制板,就是指兩層以上的印制板,它是由幾層絕緣基板上的連接導線和裝配焊接電子元件用的焊盤組成,既具有導通各層線路,又具有相互間絕緣的作用。隨著SMT(表面安裝技術)的不斷發(fā)展,以及新一代SMD(表面安裝器件)的不斷推出,如QFP、QFN、CSP、BGA(特別是MBGA),使電子產(chǎn)品更加智能化、小型化,因而推動了PCB工業(yè)技術的重大改革和進步。自1991年IBM公司首先成功開發(fā)出高密度多層板(SLC)以來,各國各大集團也相繼開發(fā)出各種各樣的高密度互連(HDI)微孔板。這些加工技術的迅猛發(fā)展,促使了PCB的設計已逐漸向多層、高密度布線的方向發(fā)展。多層印制板以其設計靈活、穩(wěn)定可靠的電氣性能和優(yōu)越的經(jīng)濟性能,現(xiàn)已廣泛應用于電子產(chǎn)品的生產(chǎn)制造中。下面,作者以多年設計印制板的經(jīng)驗,著重印制板的電氣性能,結合工藝要求,從印制板穩(wěn)定性、可靠性方面,來談談多層制板設計的基本要領。

    標簽: 多層 印制板

    上傳時間: 2013-10-08

    上傳用戶:zhishenglu

  • 高性能覆銅板的發(fā)展趨勢及對環(huán)氧樹脂性能的新需求

    討論、研究高性能覆銅板對它所用的環(huán)氧樹脂的性能要求,應是立足整個產(chǎn)業(yè)鏈的角度去觀察、分析。特別應從HDI多層板發(fā)展對高性能CCL有哪些主要性能需求上著手研究。HDI多層板有哪些發(fā)展特點,它的發(fā)展趨勢如何——這都是我們所要研究的高性能CCL發(fā)展趨勢和重點的基本依據(jù)。而HDI多層板的技術發(fā)展,又是由它的應用市場——終端電子產(chǎn)品的發(fā)展所驅動(見圖1)。 圖1 在HDI多層板產(chǎn)業(yè)鏈中各類產(chǎn)品對下游產(chǎn)品的性能需求關系圖 1.HDI多層板發(fā)展特點對高性能覆銅板技術進步的影響1.1 HDI多層板的問世,對傳統(tǒng)PCB技術及其基板材料技術是一個嚴峻挑戰(zhàn)20世紀90年代初,出現(xiàn)新一代高密度互連(High Density Interconnection,簡稱為 HDI)印制電路板——積層法多層板(Build—Up Multiplayer printed board,簡稱為 BUM)的最早開發(fā)成果。它的問世是全世界幾十年的印制電路板技術發(fā)展歷程中的重大事件。積層法多層板即HDI多層板,至今仍是發(fā)展HDI的PCB的最好、最普遍的產(chǎn)品形式。在HDI多層板之上,將最新PCB尖端技術體現(xiàn)得淋漓盡致。HDI多層板產(chǎn)品結構具有三大突出的特征:“微孔、細線、薄層化”。其中“微孔”是它的結構特點中核心與靈魂。因此,現(xiàn)又將這類HDI多層板稱作為“微孔板”。HDI多層板已經(jīng)歷了十幾年的發(fā)展歷程,但它在技術上仍充滿著朝氣蓬勃的活力,在市場上仍有著前程廣闊的空間。

    標簽: 性能 發(fā)展趨勢 覆銅板 環(huán)氧樹脂

    上傳時間: 2013-11-19

    上傳用戶:zczc

  • pci e PCB設計規(guī)范

    This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.  

    標簽: pci PCB 設計規(guī)范

    上傳時間: 2014-01-24

    上傳用戶:s363994250

  • *** *** *** *** *** *** *** *** *** *** *** *** *** *** *** *** *** *** ** RELEASE NOTES *** *** *

    *** *** *** *** *** *** *** *** *** *** *** *** *** *** *** *** *** *** ** RELEASE NOTES *** *** *** *** ***** *** *** *** *** *** *** *** *** *** *** *** *** *** 1) RELEASE NOTES: --- --- ---- The release notes are now provided in PDF format in the file: \SOFTWARE\uCOS-II\DOC\RelV251.PDF 2) FEATURES SINCE V2.00: --- --- --- ----- All the features added since V2.00 are described in the PDF file: \SOFTWARE\uCOS-II\DOC\NewV251.PDF 3) EVENT FLAGS: -------------- Event Flags are discussed in AN-1007 (see www.Micrium.com/app_notes.htm) 4) QUICK REFERENCE CHART: ------------------------ A Quick Reference Chart for all the functions in V2.51 is provided in the following .PDF files: \SOFTWARE\uCOS-II\DOC\QuickRefChartV251-Color.PDF Once printed, simply FOLD the page in half and if you have a LAMINATION machine, you can protect the chart by laminating it.

    標簽: RELEASE NOTES

    上傳時間: 2015-04-06

    上傳用戶:zq70996813

  • Preliminary User’s Manual NU85ET 32-Bit Microprocessor Core Hardware Document No. A15015EJ3V0UM0

    Preliminary User’s Manual NU85ET 32-Bit Microprocessor Core Hardware Document No. A15015EJ3V0UM00 (3rd edition) Date Published March 2002 N CP(N) printed in Japan © 2000 NU85ET NDU85ETV14

    標簽: Microprocessor Preliminary Document Hardware

    上傳時間: 2014-01-11

    上傳用戶:pompey

  • ARM下 Implement matrix multiplication of 2 square matrices, with data read from an input file and pri

    ARM下 Implement matrix multiplication of 2 square matrices, with data read from an input file and printed both to the console and to an output file. • Assume a file with correct data (no garbage, characters, etc.). • you must check and provide appropriate execution for 2 extra cases, namely when the matrix size given is either “0” , or when the size is greater than the maximum handled of “5” . In these 2 cases you must implement the following behaviour: o If size = 0, then print a message “Size = 0 is unacceptable” and continue by reading the next size for the next 2 matrices (if not end of file). o If size >5, then print two messages: “Size is too big - unacceptable”. Then read and discard the next (size2 ) integers and continue by reading the next size for the next 2 matrices (if not end of file).

    標簽: multiplication Implement matrices matrix

    上傳時間: 2014-08-30

    上傳用戶:dsgkjgkjg

  • GTRACK Track mouse position and show coordinates in figure title. Once GTRACK is active the mouse

    GTRACK Track mouse position and show coordinates in figure title. Once GTRACK is active the mouse position is constantly tracked and printed on the current figure title. A left-click will print the coordinates in the command line and store them. Clicking the mouse right button deactivates GTRACK.

    標簽: GTRACK mouse coordinates position

    上傳時間: 2013-12-17

    上傳用戶:Zxcvbnm

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