<center id="yyia2"></center> 提出一種基于C8051F040的炮塔方位角測試系統(tǒng)的設(shè)計(jì)方案，給出測試系統(tǒng)的各個(gè)模塊軟硬件設(shè)計(jì)。炮塔方位角測試系統(tǒng)集數(shù)據(jù)采集，數(shù)據(jù)傳輸和數(shù)據(jù)顯示等功能于一體，實(shí)現(xiàn)了炮塔方位角裝置的離線檢測。系統(tǒng)軟件采用C51編寫，對單片機(jī)進(jìn)行有效電源管理，保證了系統(tǒng)的穩(wěn)定性，可靠性。 Abstract: This paper puts forwards a design of artillery position system based on C8051F040，describes all modules hardware and software design of measurement system.The system has the function of information collection，transmission，and display.It can measure artillery position system in offline.The system software using C51can manage the power of single chip microcomputer，guarantee the stability，reliability.
標(biāo)簽： C8051F040 方位角 測試系統(tǒng)
上傳時(shí)間： 2014-12-27
上傳用戶：7891
提出了一種基于C8051F320的列車安全巡檢儀的設(shè)計(jì)方案，詳細(xì)闡述了巡檢儀的各個(gè)模塊的硬、軟件設(shè)計(jì)。巡檢儀集信息采集、軸溫檢測、照明和記錄存儲等功能于一體，實(shí)現(xiàn)了對列車安全巡檢工作有效的監(jiān)督和科學(xué)管理。系統(tǒng)軟件采用C51編寫，對單片機(jī)進(jìn)行有效的電源管理，保證了巡檢儀的穩(wěn)定性、可靠性和低功耗性。 Abstract: This paper puts forward a design of train safety inspection based on C8051F320,describes all modules hardware and software design of inspection instrument.The inspection instrument has the function of information collection, axle’s temperature detection, lighting and records storage.It can supervise and administer train safety inspection work effectively.The system software using C51 can manage the power of single chip microcomputer, and guarantee the stability, reliability and low power consumption of the inspection instrument.
標(biāo)簽： C8051F320 列車 儀的設(shè)計(jì) 巡檢
上傳時(shí)間： 2013-12-22
上傳用戶：落花無痕
I2C interface, is a very powerful tool for system designers. Theintegrated protocols allow systems to be completely software defined.Software development time of different products can be reduced byassembling a library of reusable software modules. In addition, themultimaster capability allows rapid testing and alignment ofend-products via external connections to an assembly-line computer.The mask programmable 87LPC76X and its EPROM version, the87LPC76X, can operate as a master or a slave device on the I2Csmall area network. In addition to the efficient interface to thededicated function ICs in the I2C family, the on-board interfacefacilities I/O and RAM expansion, access to EEPROM andprocessor-to-processor communications.
標(biāo)簽： microcontro Using 76X LPC
上傳時(shí)間： 2013-12-30
上傳用戶：Artemis
提出了一個(gè)由AT89C52單片機(jī)控制步進(jìn)電機(jī)的實(shí)例?？梢酝ㄟ^鍵盤輸入相關(guān)數(shù)據(jù), 并根據(jù)需要, 實(shí)時(shí)對步進(jìn)電機(jī)工作方式進(jìn)行設(shè)置, 具有實(shí)時(shí)性和交互性的特點(diǎn)。該系統(tǒng)可應(yīng)用于步進(jìn)電機(jī)控制的大多數(shù)場合。實(shí)踐表明, 系統(tǒng)性能優(yōu)于傳統(tǒng)的步進(jìn)電機(jī)控制器。關(guān)鍵詞: 單片機(jī); 步進(jìn)電動機(jī); 直流固態(tài)繼電器; 實(shí)時(shí)控制Con trol System of Stepp ingMotor Ba sed on AT89C52 ChipM icrocomputerMENGWu2sheng, L ILiang (College of Automatization, Northwestern Polytechnical Unversity, Xipan 710072, China)ABSTRACT: A stepp ing motor control system based on AT89C52 chip microcomputer was described.The data can be inputwith keyboard, and stepp ingmotorwas controlled by these data. According to the demand, users can set the workingmodel of stepp ingmotor in real2time. This system can be widely used in stepp ing motor controlling. The p ractice showed that the performance of this system outdid the tradi tional stepp ing motor controller.KEY WORDS: Chip microcomputer; Stepp ingmotor; DCSSR; Real2time control
標(biāo)簽： Control System ingMot Stepp
上傳時(shí)間： 2013-11-19
上傳用戶：leesuper
The Linux Programming Interface - A Linux and UNIX System
標(biāo)簽： Programming Linux Interface Handbook
上傳時(shí)間： 2013-11-10
上傳用戶：asdstation
ARM embeded system designer,周立功版本，國內(nèi)較有名的一版。
標(biāo)簽： designer embeded system ARM
上傳時(shí)間： 2013-10-31
上傳用戶：zaizaibang
完整性高的FPGA-PCB系統(tǒng)化協(xié)同設(shè)計(jì)工具 Cadence OrCAD and Allegro FPGA System Planner便可滿足較復(fù)雜的設(shè)計(jì)及在設(shè)計(jì)初級產(chǎn)生最佳的I/O引腳規(guī)劃，并可透過FSP做系統(tǒng)化的設(shè)計(jì)規(guī)劃，同時(shí)整合logic、schematic、PCB同步規(guī)劃單個(gè)或多個(gè)FPGA pin的最佳化及l(fā)ayout placement，借由整合式的界面以減少重復(fù)在design及PCB Layout的測試及修正的過程及溝通時(shí)間，甚至透過最佳化的pin mapping、placement后可節(jié)省更多的走線空間或疊構(gòu)。 Specifying Design Intent 在FSP整合工具內(nèi)可直接由零件庫選取要擺放的零件，而這些零件可直接使用PCB內(nèi)的包裝，預(yù)先讓我們同步規(guī)劃FPGA設(shè)計(jì)及在PCB的placement。
標(biāo)簽： Allegro Planner System FPGA
上傳時(shí)間： 2013-11-06
上傳用戶：wwwe
完整性高的FPGA-PCB系統(tǒng)化協(xié)同設(shè)計(jì)工具 Cadence OrCAD and Allegro FPGA System Planner便可滿足較復(fù)雜的設(shè)計(jì)及在設(shè)計(jì)初級產(chǎn)生最佳的I/O引腳規(guī)劃，并可透過FSP做系統(tǒng)化的設(shè)計(jì)規(guī)劃，同時(shí)整合logic、schematic、PCB同步規(guī)劃單個(gè)或多個(gè)FPGA pin的最佳化及l(fā)ayout placement，借由整合式的界面以減少重復(fù)在design及PCB Layout的測試及修正的過程及溝通時(shí)間，甚至透過最佳化的pin mapping、placement后可節(jié)省更多的走線空間或疊構(gòu)。 Specifying Design Intent 在FSP整合工具內(nèi)可直接由零件庫選取要擺放的零件，而這些零件可直接使用PCB內(nèi)的包裝，預(yù)先讓我們同步規(guī)劃FPGA設(shè)計(jì)及在PCB的placement。
標(biāo)簽： Allegro Planner System FPGA
上傳時(shí)間： 2013-10-19
上傳用戶：shaojie2080
本文簡單討論并總結(jié)了VHDL、Verilog，System verilog 這三中語言的各自特點(diǎn)和區(qū)別As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.
標(biāo)簽： Verilog verilog System VHDL
上傳時(shí)間： 2014-03-03
上傳用戶：zhtzht
主機(jī)氣缸油注油器說明書，Alpha Lubricator System Operation (ALCU) manual MC Engines。
標(biāo)簽： Lubricator Operation Engines System
上傳時(shí)間： 2013-10-17
上傳用戶：ynzfm
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