Advanced Design System 2019 射頻、微波和信號(hào)完整性仿真軟件 安裝包。文件較大,存在百度網(wǎng)盤,下載文件中提供了鏈接和提取碼。打開即可下載。
標(biāo)簽： ADS
上傳時(shí)間： 2022-07-10
上傳用戶：qdxqdxqdxqdx
ADS電子設(shè)計(jì)自動(dòng)化（EDA軟件全稱為 Advanced Design System，是美國(guó)安捷倫（Agilent）公司所生產(chǎn)擁有的電子設(shè)計(jì)自動(dòng)化軟件；ADS功能十分強(qiáng)大，包含時(shí)域電路仿真 (SPICE-like Simulation)、頻域電路仿真 (Harmonic Balance、Linear Analysis)、三維電磁仿真 、通信系統(tǒng)仿真(Communication System Simulation)和數(shù)字信號(hào)處理仿真設(shè)計(jì)（DSP）；支持射頻和系統(tǒng)設(shè)計(jì)工程師開發(fā)所有類型的 RF設(shè)計(jì)，從離散的射頻/微波模塊到用于通信和航天/國(guó)防的集成MMIC，是當(dāng)今國(guó)內(nèi)各大學(xué)和研究所使用最多的微波/射頻電路和通信系統(tǒng)仿真軟件軟件。
上傳時(shí)間： 2013-07-21
上傳用戶：eeworm
The DSP Design Flow workshop provides an introduction to the advanced tools you need to design and implement DSP algorithms targeting FPGAs. This intermediate workshop in implementing DSP functions focuses on learning how to use System Generator for DSP,
標(biāo)簽： workshop provides Design Flow
上傳時(shí)間： 2013-09-02
上傳用戶：joheace
本文簡(jiǎn)單討論并總結(jié)了VHDL、Verilog，System verilog 這三中語言的各自特點(diǎn)和區(qū)別As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.
標(biāo)簽： Verilog verilog System VHDL
上傳時(shí)間： 2013-10-16
上傳用戶：牛布牛
介紹了MPC555與CS8900A擴(kuò)展以太網(wǎng)的硬件設(shè)計(jì)圖。以NUCLUES PLUS操作系統(tǒng)為基礎(chǔ)，介紹了網(wǎng)卡軟件驅(qū)動(dòng)程序的編制，給出了以太網(wǎng)協(xié)議包嵌入NUCLEUS PLUS操作系統(tǒng)的實(shí)現(xiàn)方法。 Abstract: The Ethernet extension hardware design of MPC555 and CS8900A are introduced,and the software driven program based on NUCLEUS PLUS operation system and the technique that Ethernet protocol embedded in NUCLEUS PLUS real operation system are discussed.
上傳時(shí)間： 2013-10-23
上傳用戶：xiehao13
The introduction of Spartan-3™ devices has createdmultiple changes in the evolution of embedded controldesigns and pushed processing capabilities to the “almostfreestage.” With these new FPGAs falling under $20, involume, with over 1 million system gates, and under $5for 100K gate-level units, any design with programmablelogic has a readily available 8- or 16-bit processor costingless than 75 cents and 32-bit processor for less than $1.50.
上傳時(shí)間： 2013-12-10
上傳用戶：zgu489
針對(duì)嵌入式機(jī)器視覺系統(tǒng)向獨(dú)立化、智能化發(fā)展的要求，介紹了一種嵌入式視覺系統(tǒng)--智能相機(jī)。基于對(duì)智能相機(jī)體系結(jié)構(gòu)、組成模塊和圖像采集、傳輸和處理技術(shù)的分析，對(duì)國(guó)內(nèi)外的幾款智能相機(jī)進(jìn)行比較。綜合技術(shù)發(fā)展現(xiàn)狀，提出基于FPGA+DSP模式的硬件平臺(tái)，并提出智能相機(jī)的發(fā)展方向。分析結(jié)果表明，該系統(tǒng)設(shè)計(jì)可以實(shí)現(xiàn)脫離PC運(yùn)行，完成圖像獲取與分析，并作出相應(yīng)輸出。 Abstract: This paper introduced an embedded vision system-intelligent camera ，which was for embedded machine vision systems to an independent and intelligent development requirements. Intelligent camera architecture， component modules and image acquisition， transmission and processing technology were analyzed. After comparing integrated technology development of several intelligent cameras at home and abroad， the paper proposed the hardware platform based on FPGA+DSP models and made clear direction of development of intelligent cameras. On the analysis of the design， the results indicate that the system can run from the PC independently to complete the image acquisition and analysis and give a corresponding output.
標(biāo)簽： FPGA DSP 模式 智能相機(jī)
上傳時(shí)間： 2013-10-24
上傳用戶：bvdragon
The use of the Wind River VxWorks Real-Time Operating System (RTOS) on Virtex™-4embedded PowerPC™ processors continues to be a popular choice for high performanceFPGA designs. The introduction of the Wind River Workbench design environment has enableda new and easier way for designers to control the configuration of the VxWorks kernel. Thisguide shows the steps required to build and configure a ML403 Embedded DevelopmentPlatform to boot and run the VxWorks RTOS. A VxWorks bootloader is created, programmedinto Flash, and used to boot the design. The concepts presented here can be scaled to anyPowerPC enabled development platform.
上傳時(shí)間： 2013-10-26
上傳用戶：agent
提出了一種以ARM微處理器為控制核心的遠(yuǎn)程無線視頻監(jiān)控終端的設(shè)計(jì)方案，其監(jiān)控終端的硬件設(shè)計(jì)包括視頻采集處理、中央管理控制、無線傳輸3個(gè)模塊。并給出了監(jiān)控終端的軟件開發(fā)平臺(tái)和開發(fā)模式的系統(tǒng)啟動(dòng)代碼、嵌入式Linux系統(tǒng)移植以及驅(qū)動(dòng)程序和應(yīng)用程序。測(cè)試結(jié)果表明，該監(jiān)控終端設(shè)計(jì)方案合理、有效，基本滿足監(jiān)控需求。 Abstract: A remote wireless video monitoring terminal design， which uses ARM microprocessor as its core control， is proposed in this paper.The hardware design of monitoring terminal system is composed of the video acquisition and processing module， the central management and control module， wireless transmission module.Meanwhile the monitoring terminal-s software development platform and development patterns are designed. Also the design of the system-s start codes， embedded Linux system-s transplantation process， driver and the corresponding applications are given. The results showed that the monitoring terminal design is reasonable， effective， basically meet monitoring requirements.
標(biāo)簽： ARM 遠(yuǎn)程無線 視頻監(jiān)控 終端設(shè)計(jì)
上傳時(shí)間： 2013-11-13
上傳用戶：wanqunsheng
完整性高的FPGA-PCB系統(tǒng)化協(xié)同設(shè)計(jì)工具 Cadence OrCAD and Allegro FPGA System Planner便可滿足較復(fù)雜的設(shè)計(jì)及在設(shè)計(jì)初級(jí)產(chǎn)生最佳的I/O引腳規(guī)劃，并可透過FSP做系統(tǒng)化的設(shè)計(jì)規(guī)劃，同時(shí)整合logic、schematic、PCB同步規(guī)劃單個(gè)或多個(gè)FPGA pin的最佳化及l(fā)ayout placement，借由整合式的界面以減少重復(fù)在design及PCB Layout的測(cè)試及修正的過程及溝通時(shí)間，甚至透過最佳化的pin mapping、placement后可節(jié)省更多的走線空間或疊構(gòu)。 Specifying Design Intent 在FSP整合工具內(nèi)可直接由零件庫選取要擺放的零件，而這些零件可直接使用PCB內(nèi)的包裝，預(yù)先讓我們同步規(guī)劃FPGA設(shè)計(jì)及在PCB的placement。
標(biāo)簽： Allegro Planner System FPGA
上傳時(shí)間： 2013-11-06
上傳用戶：wwwe
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