With the advent of IMT-2000, CDMA has emerged at the focal point of interest in wireless communications. Now it has become impossible to discuss wireless communications without knowing the CDMA technologies. There are a number of books readily published on the CDMA technologies, but they are mostly dealing with the traditional spread-spectrum technologies and the IS-95 based CDMA systems. As a large number of novel and interesting technologies have been newly developed throughout the IMT-2000 standardization process in very recent years, new reference books are now demanding that address the diverse spectrum of the new CDMA technologies.
標(biāo)簽： Communications Scrambling Techniques CDMA for
上傳時(shí)間： 2020-06-01
上傳用戶：shancjb
RFID is at a critical price point that could enable its large-scale adoption. What strengths are pushing it forward? What technical challenges and privacy concerns must we still address?
標(biāo)簽： an-introduction-to-rfid-technolog
上傳時(shí)間： 2020-06-08
上傳用戶：shancjb
Human Factors and Systems Interaction aims to address the main issues of concern within systems interface with a particular emphasis on the system lifecycle development and implementation of interfaces and the general implications of virtual, augmented and mixed reality with respect to human and technology interaction. Human Factors and Systems Interaction is, in the first instance, affected by the forces shaping the nature offuture computing and systems development
標(biāo)簽： Interactions Advances Factors System Human and in
上傳時(shí)間： 2020-06-10
上傳用戶：shancjb
THIS PUBLICATION IS COPYRIGHT PROTECTEDCopyright ? 2014 IEC, Geneva, SwitzerlandAll rights reserved. Unless otherwise specified, no part of this publication may be reproduced or utilized in any formor by any means, electronic or mechanical, including photocopying and microfilm, without permission in writing fromeither IEC or IEC's member National Committee in the country of the requester. If you have any questions about IECcopyright or have an enquiry about obtaining additional rights to this publication, please contact the address below oryour local IEC member National Committee for further information.Droits de reproduction réservés. Sauf indication contraire, aucune partie de cette publication ne peut être reproduiteni utilisée sous quelque forme que ce soit et par aucun procédé, électronique ou mécanique, y compris la photocopieet les microfilms, sans l'accord écrit de l'IEC ou du Comité national de l'IEC du pays du demandeur. Si vous avez desquestions sur le copyright de l'IEC ou si vous désirez obtenir des droits supplémentaires sur cette publication, utilisezles coordonnées ci-après ou contactez le Comité national de l'IEC de votre pays de résidence.
標(biāo)簽： iec標(biāo)準(zhǔn)
上傳時(shí)間： 2021-10-21
上傳用戶：kent
FPGA讀寫SD卡讀取BMP圖片通過(guò)LCD顯示例程實(shí)驗(yàn) Verilog邏輯源碼Quartus工程文件+文檔說(shuō)明,FPGA型號(hào)Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。1 實(shí)驗(yàn)簡(jiǎn)介在前面的實(shí)驗(yàn)中我們練習(xí)了 SD 卡讀寫，VGA 視頻顯示等例程，本實(shí)驗(yàn)將 SD 卡里的 BMP 圖片讀出，寫入到外部存儲(chǔ)器，再通過(guò) VGA、LCD 等顯示。本實(shí)驗(yàn)如果通過(guò)液晶屏顯示，需要有液晶屏模塊。2 實(shí)驗(yàn)原理在前面的實(shí)驗(yàn)中我們?cè)?VGA、LCD 上顯示的是彩條，是 FPGA 內(nèi)部產(chǎn)生的數(shù)據(jù)，本實(shí)驗(yàn)將彩條替換為 SD 內(nèi)的 BMP 圖片數(shù)據(jù)，但是 SD 卡讀取速度遠(yuǎn)遠(yuǎn)不能滿足顯示速度的要求，只能先寫入外部高速 RAM，再讀出后給視頻時(shí)序模塊顯示module top( input clk, input rst_n, input key1, output [5:0] seg_sel, output [7:0] seg_data, output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sd_ncs, //SD card chip select (SPI mode) output sd_dclk, //SD card clock output sd_mosi, //SD card controller data output input sd_miso, //SD card controller data input output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24
標(biāo)簽： fpga
上傳時(shí)間： 2021-10-27
上傳用戶：
IIC接口E2PROM(AT24C64) 讀寫VERILOG 驅(qū)動(dòng)源碼+仿真激勵(lì)文件:module i2c_dri #( parameter SLAVE_ADDR = 7'b1010000 , //EEPROM從機(jī)地址 parameter CLK_FREQ = 26'd50_000_000, //模塊輸入的時(shí)鐘頻率 parameter I2C_FREQ = 18'd250_000 //IIC_SCL的時(shí)鐘頻率 ) ( input clk , input rst_n , //i2c interface input i2c_exec , //I2C觸發(fā)執(zhí)行信號(hào) input bit_ctrl , //字地址位控制(16b/8b) input i2c_rh_wl , //I2C讀寫控制信號(hào) input [15:0] i2c_addr , //I2C器件內(nèi)地址 input [ 7:0] i2c_data_w , //I2C要寫的數(shù)據(jù) output reg [ 7:0] i2c_data_r , //I2C讀出的數(shù)據(jù) output reg i2c_done , //I2C一次操作完成 output reg i2c_ack , //I2C應(yīng)答標(biāo)志 0:應(yīng)答 1:未應(yīng)答 output reg scl , //I2C的SCL時(shí)鐘信號(hào) inout sda , //I2C的SDA信號(hào) //user interface output reg dri_clk //驅(qū)動(dòng)I2C操作的驅(qū)動(dòng)時(shí)鐘 );//localparam definelocalparam st_idle = 8'b0000_0001; //空閑狀態(tài)localparam st_sladdr = 8'b0000_0010; //發(fā)送器件地址(slave address)localparam st_addr16 = 8'b0000_0100; //發(fā)送16位字地址localparam st_addr8 = 8'b0000_1000; //發(fā)送8位字地址localparam st_data_wr = 8'b0001_0000; //寫數(shù)據(jù)(8 bit)localparam st_addr_rd = 8'b0010_0000; //發(fā)送器件地址讀localparam st_data_rd = 8'b0100_0000; //讀數(shù)據(jù)(8 bit)localparam st_stop = 8'b1000_0000; //結(jié)束I2C操作//reg definereg sda_dir ; //I2C數(shù)據(jù)(SDA)方向控制reg sda_out ; //SDA輸出信號(hào)reg st_done ; //狀態(tài)結(jié)束reg wr_flag ; //寫標(biāo)志reg [ 6:0] cnt ; //計(jì)數(shù)reg [ 7:0] cur_state ; //狀態(tài)機(jī)當(dāng)前狀態(tài)reg [ 7:0] next_state; //狀態(tài)機(jī)下一狀態(tài)reg [15:0] addr_t ; //地址reg [ 7:0] data_r ; //讀取的數(shù)據(jù)reg [ 7:0] data_wr_t ; //I2C需寫的數(shù)據(jù)的臨時(shí)寄存reg [ 9:0] clk_cnt ; //分頻時(shí)
標(biāo)簽： iic 接口 e2prom at24c64 verilog 驅(qū)動(dòng) 仿真
上傳時(shí)間： 2021-11-05
上傳用戶：
This book addresses programmer attitudes, but it’s not some kind of psychology textbook. We’ll investigate many topics, including: Source code presentation Defensive coding techniques How to debug programs effectively Good teamworking skills Managing your source code Take a quick glance through the table of contents to see exactly what’s covered. What is the rationale behind my selection of topics? I’ve been mentor- ing trainee programmers for many years, and these are the topics that have come up time and time again. I’ve also worked in the software factory for long enough to have seen the recurring problems—I address these too. If you can conquer all of these programming demons, you’ll progress from an apprentice coder to a real code craftsman.
標(biāo)簽： excellent practice writing Craft Code code the of
上傳時(shí)間： 2021-11-09
上傳用戶：danix800
FPGA讀取OV5640攝像頭數(shù)據(jù)并通過(guò)VGA或LCD屏顯示輸出的Verilog邏輯源碼Quartus工程文件+文檔說(shuō)明，F(xiàn)PGA型號(hào)Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, output cmos_scl, //cmos i2c clock inout cmos_sda, //cmos i2c data input cmos_vsync, //cmos vsync input cmos_href, //cmos hsync refrence,data valid input cmos_pclk, //cmos pxiel clock output cmos_xclk, //cmos externl clock input [7:0] cmos_db, //cmos data output cmos_rst_n, //cmos reset output cmos_pwdn, //cmos power down output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);
上傳時(shí)間： 2021-12-18
上傳用戶：
基于FPGA設(shè)計(jì)的sdram讀寫測(cè)試實(shí)驗(yàn)Verilog邏輯源碼Quartus工程文件+文檔說(shuō)明，DRAM選用海力士公司的 HY57V2562 型號(hào),容量為的 256Mbit,采用了 54 引腳的TSOP 封裝, 數(shù)據(jù)寬度都為 16 位, 工作電壓為 3.3V,并丏采用同步接口方式所有的信號(hào)都是時(shí)鐘信號(hào)。FPGA型號(hào)Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ps/1psmodule top(input clk,input rst_n,output[1:0] led,output sdram_clk, //sdram clockoutput sdram_cke, //sdram clock enableoutput sdram_cs_n, //sdram chip selectoutput sdram_we_n, //sdram write enableoutput sdram_cas_n, //sdram column address strobeoutput sdram_ras_n, //sdram row address strobeoutput[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank addressoutput[12:0] sdram_addr, //sdram addressinout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24 ; //external memory user interface address widthparameter BUSRT_BITS = 10 ; //external memory user interface burst widthparameter BURST_SIZE = 128 ; //burst sizewire wr_burst_data_req; // from external memory controller,write data request ,before data 1 clockwire wr_burst_finish; // from external memory controller,burst write finish
標(biāo)簽： fpga sdram verilog quartus
上傳時(shí)間： 2021-12-18
上傳用戶：
This manual documents the Microcontroller profile of version 7 of the ARM? Architecture, the ARMv7-M architecture profile. For short definitions of all the ARMv7 profiles see About the ARMv7 architecture, and architecture profiles on page A1-20.ARMv7 is documented as a set of architecture profiles. The profiles are defined as follows: ARMv7-A The application profile for systems supporting the ARM and Thumb instruction sets, and requiring virtual address support in the memory management model. ARMv7-R The realtime profile for systems supporting the ARM and Thumb instruction sets, and requiring physical address only support in the memory management model ARMv7-M The microcontroller profile for systems supporting only the Thumb instruction set, and where overall size and deterministic operation for an implementation are more important than absolute performance. While profiles were formally introduced with the ARMv7 development, the A-profile and R-profile have implicitly existed in earlier versions, associated with the Virtual Memory System Architecture (VMSA) and Protected Memory System Architecture (PMSA) respectively.
標(biāo)簽： arm
上傳時(shí)間： 2022-06-02
上傳用戶：
蟲(chóng)蟲(chóng)下載站版權(quán)所有 京ICP備2021023401號(hào)-1
