講述未來無線通信soc的設計方法，要點和未來的發展趨勢
上傳時間： 2013-12-27
上傳用戶：xiaoyunyun
---- ---- ---- WISHBONE Wishbone_BFM IP Core ---- ---- ---- ---- This file is part of the Wishbone_BFM project ---- ---- http://www.opencores.org/cores/Wishbone_BFM/ ---- ---- ---- ---- Description ---- ---- Implementation of Wishbone_BFM IP core according to ---- ---- Wishbone_BFM IP core specification document.
標簽： Wishbone_BFM WISHBONE Wishbon Core
上傳時間： 2016-09-04
上傳用戶：lanjisu111
i.mx27 soc for wince 6.0
上傳時間： 2016-09-05
上傳用戶：xjz632
LCD Driver datasheet The SPF54126A, a 262144-color System-on-Chip (SoC) driver LSI designed for small and medium sizes of TFT LCD display, is capable of supporting up to 176xRGBx220 in resolution which can be achieved by the designated RAM for graphic data. The 528-channel source driver has true 6-bit resolution, which generates 64 Gamma-corrected values by an internal D/A converter. The source driver of SPFD54126A adopts OP-AMP structure to enhance display quality and it cooperates with advanced circuitry techniques to reduce power consumption.
標簽： System-on-Chip datasheet designed Driver
上傳時間： 2016-09-22
上傳用戶：xauthu
ili9320 datasheet. ILI9320 is a 262,144-color one-chip SoC driver for a-TFT liquid crystal display with resolution of 240RGBx320 dots, comprising a 720-channel source driver, a 320-channel gate driver, 172,800 bytes RAM for graphic data of 240RGBx320 dots, and power supply circuit.
標簽： 9320 datasheet one-chip crystal
上傳時間： 2014-11-21
上傳用戶：jiahao131
Linux uart driver for Infineon ADM5120 SOC Uart port. This is good reference to operate the SOC uart port.
標簽： uart SOC reference Infineon
上傳時間： 2016-09-26
上傳用戶：lgnf
V9001單相電能計量SoC提供單相電能表的單片解決方案，可以大幅簡化電能表設計，降低系統成本，并縮短產品上市時間： 集成高精度Σ/ΔADC集成高精度，多功能電能計量DSP電路，集成高性能微控制器MCU
上傳時間： 2014-12-22
上傳用戶：asdfasdfd
// -*- Mode: Verilog -*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISHBONE Master // Supported cycles: MASTER, READ/WRITE // MASTER, BLOCK READ/WRITE // MASTER, RMW // Data port, size: 8, 16, 32-bit // Data port, granularity 8-bit // Data port, Max. operand size 32-bit // Data transfer ordering: little endian // Data transfer sequencing: undefined
標簽： Description Behavorial wb_master Filename
上傳時間： 2014-07-11
上傳用戶：zhanditian
Introduce the wishbone bus .
標簽： Introduce wishbone the bus
上傳時間： 2013-11-28
上傳用戶：lacsx
用于SoC設計的DFT和BIST，講解了在SOC設計中需要考慮的可測性設計問題
上傳時間： 2016-10-28
上傳用戶：亞亞娟娟123
