Abstract: While many questions still surround the creation and deployment of the smart grid, the need for a reliablecommunications infrastructure is indisputable. Developers of the IEEE 1901.2 standard identified difficult channel conditionscharacteristic of low-frequency powerline communications and implemented an orthogonal frequency division multiplexing (OFDM)architecture using advanced modulation and channel-coding techniques. This strategy helped to ensure a robust communicationsnetwork for the smart grid.
One of the most misunderstood constructs in the Verilog language is the nonblockingassignment. Even very experienced Verilog designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant Verilog simulator and do not understand whenand why nonblocking assignments should be used. This paper details how Verilog blocking andnonblocking assignments are scheduled, gives important coding guidelines to infer correctsynthesizable logic and details coding styles to avoid Verilog simulation race conditions
為了提高直接轉矩控制(DTC)系統定子磁鏈估計精度,降低電流、電壓測量的隨機誤差,提出了一種基于擴展卡爾曼濾波(EKF)實現異步電機轉子位置和速度估計的方法。擴展卡爾曼濾波器是建立在基于旋轉坐標系下由定子電流、電壓、轉子轉速和其它電機參量所構成的電機模型上,將定子電流、定子磁鏈、轉速和轉子角位置作為狀態變量,定子電壓為輸入變量,定子電流為輸出變量,通過對磁鏈和轉速的閉環控制提高定子磁鏈的估計精度,實現了異步電機的無速度傳感器直接轉矩控制策略,仿真結果驗證了該方法的可行性,提高了直接轉矩的控制性能。
Abstract:
In order to improve the Direct Torque Control(DTC) system of stator flux estimation accuracy and reduce the current, voltage measurement of random error, a novel method to estimate the speed and rotor position of asynchronous motor based on extended Kalman filter was introduced. EKF was based on d-p axis motor and other motor parameters (state vector: stator current, stator flux linkage, rotor angular speed and position; input: stator voltage; output: staror current). EKF was designed for stator flux and rotor speed estimation in close-loop control. It can improve the estimated accuracy of stator flux. It is possible to estimate the speed and rotor position and implement asynchronous motor drives without position and speed sensors. The simulation results show it is efficient and improves the control performance.
在集成電路內建自測試的過程中,電路的測試功耗通常顯著高于正常模式產生的功耗,因此低功耗內建自測試技術已成為當前的一個研究熱點。為了減少被測電路內部節點的開關翻轉活動率,研究了一種隨機單輸入跳變(Random Single Input Change,RSIC)測試向量生成器的設計方案,利用VHDL語言描述了內建自測試結構中的測試向量生成模塊,進行了計算機模擬仿真并用FPGA(EP1C6Q240C8)加以硬件實現。實驗結果證實了這種內建自測試原理電路的正確性和有效性。