自己做的猜數字游戲， 用的是random， 很基本的一個程序
標簽： 數字
上傳時間： 2015-08-30
上傳用戶：xiaoxiang
Procedure TSPSA: begin init-of-T { T為初始溫度} S={1，……，n} {S為初始值} termination=false while termination=false begin for i=1 to L do begin generate(S′form S) { 從當前回路S產生新回路S′} Δt:=f(S′))-f(S) {f(S)為路徑總長} IF(Δt<0) OR (EXP(-Δt/T)>Random-of-[0,1]) S=S′ IF the-halt-condition-is-TRUE THEN termination=true End T_lower End End
標簽： Procedure init-of-T TSPSA begin
上傳時間： 2013-12-20
上傳用戶：shinesyh
It is possible that certain products which can be built using this software modules might form inventions protected by patent rights in some countries (e.g. by patents about arithmetic coding algorithms owned by IBM and AT&T in the USA). Provision of this software by the author does NOT include any licenses for any patents. In those countries where a patent license is required for certain applications of this software modules, you will have to obtain such a license yourself.
標簽： possible products software certain
上傳時間： 2015-09-02
上傳用戶：gut1234567
Secure Programming Cookbook for C and C++ is an important new resource for developers serious about writing secure code for Unix(including Linux) and Windows environments. This essential code companion covers a wide range of topics, including safe initialization, access control, input validation, symmetric and public key cryptography, cryptographic hashes and MACs, authentication and key exchange, PKI, random numbers, and anti-tampering.
標簽： Programming developers for important
上傳時間： 2015-09-03
上傳用戶：gundan
Perl & XML. by Erik T. Ray and Jason McIntosh ISBN 0-596-00205-X First Edition, published April 2002. (See the catalog page for this book.) Table of Contents Copyright Page Preface Chapter 1: Perl and XML Chapter 2: An XML Recap Chapter 3: XML Basics: Reading and Writing Chapter 4: Event Streams Chapter 5: SAX Chapter 6: Tree Processing Chapter 7: DOM Chapter 8: Beyond Trees: XPath, XSLT, and More Chapter 9: RSS, SOAP, and Other XML Applications Chapter 10: Coding Strategies Index Colophon --------------------------------------------------------------------------------
標簽： T. published McIntosh Edition
上傳時間： 2013-12-24
上傳用戶：yzhl1988
The EM Wave MATLAB Library consists of a collection of MATLAB programs related to electromagnetic wave scattering with special emphasis on wave scattering by random rough surfaces and discrete random media.
標簽： MATLAB electromagnetic collection consists
上傳時間： 2015-09-06
上傳用戶：alan-ee
使用到的參數跟談到彈性網絡的那一章里頭所講的是一樣的， ke 則是終止條件。如果 step 被打勾，則程式在每一步之間會暫停 100毫秒（或其他使用者輸入的數值）。如果 Random 被打勾，則程式會以系統時間作為亂數產生器的種子數，否則，就以使用者輸入的數（ Random 右邊那一格）為種子數。 你可以利用 load 來載入推銷員問題檔與其最佳解，如此便可比較彈性網絡所找出來的解與最佳解差了多少。 Central, Radius, and Error 這三個參數的前兩個，只影響彈性網絡的起使位置和大小，對求解沒有影響。第三個參數代表城市與網絡點之間的容忍距離，也就是說，如果某城市與某網絡點之間的距離，小于容忍距離，那就把這個城市當成是被該網絡點所拜訪。 按下小 w按鈕會將目前的結果與參數值寫到“en.out”這個檔案。使得我們可以很方便地來比較不同參數的效果。
上傳時間： 2013-12-17
上傳用戶：84425894
基于Verilog-HDL的硬件電路的實現 9.3 脈沖計數與顯示 9.3.1 脈沖計數器的工作原理 9.3.2 計數模塊的設計與實現 9.3.3 parameter的使用方法 9.3.4 repeat循環語句的使用方法 9.3.5 系統函數$random的使用方法 9.3.6 脈沖計數器的Verilog-HDL描述 9.3.7 特定脈沖序列的發生 9.3.8 脈沖計數器的硬件實現
標簽： Verilog-HDL parameter 9.3 硬件電路
上傳時間： 2013-12-14
上傳用戶：jeffery
This code was used for making the practical measurements in section 2.3 of my thesis. This Matlab code allows an OFDM signal to be generated based on an input data file. The data can be random data, a grey scale image, a wave file, or any type of file. The generated OFDM signal is stored as a windows wave file, allowing it to be viewed, listened to and manipulated in other programs. The modified wave file can then be decoded by the receiver software to extract the original data. This code was developed for the experiments that I performed in my honours thesis, and thus has not been fully debugged. This is the original code developed for the thesis and so has several problems with it. The BER performance given by the simulations is infact Symbol Error Rate.
標簽： This measurements practical section
上傳時間： 2015-09-20
上傳用戶：tedo811
Verilog and VHDL狀態機設計，英文pdf格式 State machine design techniques for Verilog and VHDL Abstract : Designing a synchronous finite state Another way of organizing a state machine (FSM) is a common task for a digital logic only one logic block as shown in engineer. This paper will discuss a variety of issues regarding FSM design using Synopsys Design Compiler . Verilog and VHDL coding styles will be 2.0 Basic HDL coding presented. Different methodologies will be compared using real-world examples.
上傳時間： 2013-12-19
上傳用戶：change0329
