IEEE Std 1180-1990. IEEE Standard Specifications for the Implementations of 8x8 Inverse Discrete Cosine Transform, specifies the numerical characteristics of the 8x8 inverse discrete cosine transform (IDCT) for use in visual telephony and similar applications where the 8x8 IDCT results are used in a reconstruction loop. The specifications ensure the compatibility between different implementations of the IDCT.
標簽： IEEE Implementations Specifications Discrete
上傳時間： 2016-01-31
上傳用戶：guanliya
DataDraw is an ultra-fast persistent database for high performance programs written in C. It s so fast that many programs keep all their data in a DataDraw database, even whi le being manipulated in inner loop s of compute intensive appl ications.
標簽： C. performance ultra-fast persistent
上傳時間： 2013-12-19
上傳用戶：xhz1993
// This program measures the voltage on an external ADC input and prints the // result to a terminal window via the UART. // // The system is clocked using the internal 24.5MHz oscillator. // Results are printed to the UART from a loop with the rate set by a delay // based on Timer 2. This loop periodically reads the ADC value from a global // variable, Result.
標簽： the measures external program
上傳時間： 2013-12-27
上傳用戶：trepb001
NAME: u2440mon.c DESC: u2440mon entry point,menu,download HISTORY: Mar.25.2002:purnnamu: S3C2400X profile.c is ported for S3C2410X. Mar.27.2002:purnnamu: DMA is enabled. Apr.01.2002:purnnamu: isDownloadReady flag is added. Apr.10.2002:purnnamu: - Selecting menu is available in the waiting loop. So, isDownloadReady flag gets not needed - UART ch.1 can be selected for the console. Aug.20.2002:purnnamu: revision number change 0.2 -> R1.1 Sep.03.2002:purnnamu: To remove the power noise in the USB signal, the unused CLKOUT0,1 is disabled.
標簽： 2440 mon download purnnamu
上傳時間： 2016-05-12
上傳用戶：wff
//*** *** *** *** *** *** *** *** *** *** *** *** *** * // MSP-FET430x110 Demo - Software Toggle P1.0 // // Description: Toggle P1.0 by xor ing P1.0 inside of a software loop. // ACLK = n/a, MCLK = SMCLK = default DCO ~800k // // MSP430F1121 // ----------------- // /|\| XIN|- // | | | // --|RST XOUT|- // | | // | P1.0|-->LED // // M. Buccini // Texas Instruments Inc. // Feb 2005 // Built with IAR Embedded Workbench Version: 3.21A
標簽： Software MSP-FET Toggle Demo
上傳時間： 2014-01-09
上傳用戶：問題問題
Description: The programm generates encoder for CRC-, BCH- and RS-Codes. The command line options of the tools can be displayed with -h !
標簽： Description The generates RS-Codes
上傳時間： 2016-06-25
上傳用戶：ikemada
MediaPlayer代碼，部分代碼，合適請用： import java.awt.* import java.awt.event.* import javax.swing.* import javax.media.* import java.io.* import java.util.* //為了導入Vector //import com.sun.java.swing.plaf.windows.* public class MediaPlayer extends JFrame implements ActionListener,Runnable { private JMenuBar bar //菜單條 private JMenu fileMenu,choiceMenu,aboutMenu private JMenuItem openItem,openDirItem,closeItem,about,infor private JCheckBoxMenuItem onTop private boolean top=false,loop //設定窗口是否在最前面 private Player player //Play是個實現Controller的接口 private File file,listFile //利用File類結合JFileChooser進行文件打開操作,后則與list.ini有關
標簽： MediaPlayer 代碼
上傳時間： 2016-07-08
上傳用戶：爺的氣質
ADM6993F/FXFiber to Fast Ethernet Converter (TS1000 CPE Complied) The ADM6993F/FX is a single chip integrating two 10/100 Mbps MDIX TX/FX transceivers, a three-port 10/100M Ethernet L2 switch controller, and one OAM engine to meet demanding applications, including Fiber-to-Ethernet media converters, especially the fiber to the home (FTTH) media converters. The ADM6993F/FX feature set includes link pass through (LPT), TS1000 OAM frame receiving/processing/transmitting, programmable link status LED display, various loop-back modes, and one configurable MII ports for snooping/inserting OAM frame from/to 100Fx. The ADM6993FX is the environmentally friendly “green” package version.
標簽： 6993 ADM Converter Ethernet
上傳時間： 2014-01-01
上傳用戶：hebmuljb
This GLib version 2.16.1. GLib is the low-level core library that forms the basis for projects such as GTK+ and GNOME. It provides data structure handling for C, portability wrappers, and interfaces for such runtime functionality as an event loop, threads, dynamic loading, and an object system.
標簽： GLib the low-level projects
上傳時間： 2013-12-19
上傳用戶：tb_6877751
DDR SDRAM控制器的VHDL源代碼，含詳細設計文檔。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.
上傳時間： 2014-11-01
上傳用戶：l254587896
