Very good code for Phase locked Loop in matlab
標(biāo)簽： locked matlab Phase Very
上傳時(shí)間： 2014-01-16
上傳用戶：zhuimenghuadie
通過(guò)GOTO LOOP語(yǔ)句創(chuàng)建一顆二叉樹(shù)，此代碼本人個(gè)人寫(xiě)的，通過(guò)測(cè)試合格。
上傳時(shí)間： 2017-09-17
上傳用戶：saharawalker
This work titled A Digital Phase Locked Loop based Signal and Symbol Recovery System for Wireless Channel is intended to serve as a document covering funda- mental concepts and application details related to the design of digital phase locked loop (DPLL) and its importance in wireless communication. It documents some of the work done during the last few years covering rudimentary design issues, complex implementations, and fixing configuration for a range of wireless propa- gation conditions.
標(biāo)簽： Digital Locked Phase Loop
上傳時(shí)間： 2020-05-27
上傳用戶：shancjb
CR6221 combines a dedicated current mode PWM controller with a high voltage power MOSFET. It is opti
標(biāo)簽： Current Switch Power 6221
上傳時(shí)間： 2013-04-24
上傳用戶：brucewan
CR6228 combines a dedicated current mode PWM controller with a high voltage power MOSFET. It is opti
標(biāo)簽： Current Switch Power 6228
上傳時(shí)間： 2013-05-17
上傳用戶：natopsi
Phase–locked loop (PLL) frequency synthesizers are commonlyfound in communication gear today. Th
上傳時(shí)間： 2013-04-24
上傳用戶：yxgi5
The MAX2870 ultra-wideband phase-locked loop (PLL) and voltagecontrol oscillator (VCO) can operate in both integer-N and fractional-Nmodes, similar to the Analog Devices ADF4350 wideband synthesizer.This application note compares the MAX2870 and ADF4350 registers andloop filter design in detail. Users who already familiar with ADF4350 canuse this application note as a quick design reference.
標(biāo)簽： 寄存器 環(huán)路濾波器
上傳時(shí)間： 2014-12-23
上傳用戶：變形金剛
Abstract: Many industrial/scientific/medical (ISM) band radio frequency (RF) products use crystal oscillators to generate areference for the phase-locked loop (PLL)-based local oscillator (LO). This tutorial provides a basic description of theISM-RF Crystal Calculator, which can be used to calculate various impacts on crystal frequency accuracy and startupmargin for such an LO.
上傳時(shí)間： 2013-11-15
上傳用戶：JasonC
The purpose of this application note is to show an example of how a digital potentiometer can be used in thefeedback loop of a step-up DC-DC converter to provide calibration and/or adjustment of the output voltage.The example circuit uses a MAX5025 step-up DC-DC converter (capable of generating up to 36V,120mWmax) in conjunction with a DS1845, 256 position, NV digital potentiometer. For this example, the desiredoutput voltage is 32V, which is generated from an input supply of 5V. The output voltage can be adjusted in35mV increments (near 32V) and span a range wide enough to account for resistance, potentiometer and DCDCconverter tolerances (27.6V to 36.7V).
標(biāo)簽： DC-DC 數(shù)字電位器 升壓型 校準(zhǔn)
上傳時(shí)間： 2014-12-23
上傳用戶：781354052
A complete design for a data acquisition card for the IBM PC is detailed in this application note. Additionally, C language code is provided to allow sampling of data at speed of more than 20kHz. The speed limitation is strictly based on the execution speed of the "C" data acquisition loop. A "Turbo" XT can acquire data at speeds greater than 20kHz. Machines with 80286 and 80386 processors can go faster than 20kHz. The computer that was used as a test bed in this application was an XT running at 4.77MHz and therefore all system timing and acquisition time measurements are based on a 4.77MHz clock speed.
標(biāo)簽： 1099 LTC 數(shù)據(jù) 采集板
上傳時(shí)間： 2013-10-29
上傳用戶：BOBOniu
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