This effort started as an answer to the numerous questions the authors have repeatedly had to answer about electrostatic discharge (ESD) protection and input/output (1/0) designs. In the past no comprehensive book existed suffi- ciently covering these areas, and these topics were rarely taught in engineering schools. Thus first-time I/O and ESD protection designers have had consider- able trouble getting started. This book is in part an answer to such needs.
標(biāo)簽： Design Basic ESD and IO
上傳時(shí)間： 2020-06-05
上傳用戶：shancjb
This book describes a unifying framework to networked teleoperation systems cutting across multiple research fields including networked control system for linear and nonlinear forms, bilateral teleoperation, trilateral teleoperation, multilateral teleoperation, cooperative teleoperation, and some teleoperation application examples. Networked control has been deeply studied at the intersection of systems & control and robotics for a long time, and many scholarly books on the topic have been already published. Nevertheless, the approach remains active even in several new research fields, such as bilateral teleoperation, single master and multiple slaves, trilateral teleoperation, and multilateral teleoperation
標(biāo)簽： Teleoperation Intelligent Networked Control
上傳時(shí)間： 2020-06-10
上傳用戶：shancjb
Recent work has shown that convolutional networks can be substantially deeper, more accurate, and efficient to train if they contain shorter connections between layers close to the input and those close to the output. In this paper, we embrace this observation and introduce the Dense Convo- lutional Network (DenseNet), which connects each layer to every other layer in a feed-forward fashion.
標(biāo)簽： Convolutional Connected Networks Densely
上傳時(shí)間： 2020-06-10
上傳用戶：shancjb
lm75A溫度數(shù)字轉(zhuǎn)換器 FPGA讀寫實(shí)驗(yàn)Verilog邏輯源碼Quartus工程文件+文檔資料,FPGA為CYCLONE4系列中的EP4CE6E22C8. 完整的工程文件，可以做為你的學(xué)習(xí)設(shè)計(jì)參考。LM75A 是一個(gè)使用了內(nèi)置帶隙溫度傳感器和模數(shù)轉(zhuǎn)換技術(shù)的溫度數(shù)字轉(zhuǎn)換器。它也是一個(gè)溫度檢測(cè)器，可提供一個(gè)過(guò)熱檢測(cè)輸出。LM75A 包含許多數(shù)據(jù)寄存器：配置寄存器用來(lái)存儲(chǔ)器件的某些配置，如器件的工作模式、OS 工作模式、OS 極性和OS 故障隊(duì)列等（在功能描述一節(jié)中有詳細(xì)描述）；溫度寄存器（Temp），用來(lái)存儲(chǔ)讀取的數(shù)字溫度；設(shè)定點(diǎn)寄存器（Tos & Thyst），用來(lái)存儲(chǔ)可編程的過(guò)熱關(guān)斷和滯后限制，器件通過(guò)2 線的串行I2C 總線接口與控制器通信。LM75A 還包含一個(gè)開漏輸出（OS），當(dāng)溫度超過(guò)編程限制的值時(shí)該輸出有效。LM75A 有3 個(gè)可選的邏輯地址管腳，使得同一總線上可同時(shí)連接8個(gè)器件而不發(fā)生地址沖突。LM75A 可配置成不同的工作條件。它可設(shè)置成在正常工作模式下周期性地對(duì)環(huán)境溫度進(jìn)行監(jiān)控或進(jìn)入關(guān)斷模式來(lái)將器件功耗降至最低。OS 輸出有2 種可選的工作模式：OS 比較器模式和OS 中斷模式。OS 輸出可選擇高電平或低電平有效。故障隊(duì)列和設(shè)定點(diǎn)限制可編程，為了激活OS 輸出，故障隊(duì)列定義了許多連續(xù)的故障。溫度寄存器通常存放著一個(gè)11 位的二進(jìn)制數(shù)的補(bǔ)碼，用來(lái)實(shí)現(xiàn)0.125℃的精度。這個(gè)高精度在需要精確地測(cè)量溫度偏移或超出限制范圍的應(yīng)用中非常有用。正常工作模式下，當(dāng)器件上電時(shí)，OS 工作在比較器模式，溫度閾值為80℃，滯后75℃，這時(shí)，LM75A就可用作一個(gè)具有以上預(yù)定義溫度設(shè)定點(diǎn)的獨(dú)立的溫度控制器。module LM75_SEG_LED ( //input input sys_clk ,input sys_rst_n ,inout sda_port ,//output output wire seg_c1 ,output wire seg_c2 ,output wire seg_c3 ,output wire seg_c4 ,output reg seg_a ,output reg seg_b ,output reg seg_c ,output reg seg_e ,output reg seg_d ,output reg seg_f ,output reg seg_g ,output reg seg_h , output reg clk_sclk );//parameter define parameter WIDTH = 8;parameter SIZE = 8;//reg define reg [WIDTH-1:0] counter ;reg [9:0] counter_div ;reg clk_50k ;reg clk_200k ;reg sda ;reg enable ;
標(biāo)簽： lm75a 數(shù)字轉(zhuǎn)換器 fpga verilog
上傳時(shí)間： 2021-10-27
上傳用戶：
FPGA采樣AD9238數(shù)據(jù)并通過(guò)VGA波形顯示例程 Verilog邏輯源碼Quartus工程文件+文檔說(shuō)明,FPGA型號(hào)Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。ADC 模塊型號(hào)為 AN9238，最大采樣率 65Mhz，精度為12 位。實(shí)驗(yàn)中把 AN9238 的 2 路輸入以波形方式在 HDMI 上顯示出來(lái)，我們可以用更加直觀的方式觀察波形，是一個(gè)數(shù)字示波器雛形。module top( input clk, input rst_n, output ad9238_clk_ch0, output ad9238_clk_ch1, input[11:0] ad9238_data_ch0, input[11:0] ad9238_data_ch1, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue);wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;wire grid_hs;wire grid_vs;wire grid_de;wire[7:0] grid_r;wire[7:0] grid_g;wire[7:0] grid_b;wire wave0_hs;wire wave0_vs;wire wave0_de;wire[7:0] wave0_r;wire[7:0] wave0_g;wire[7:0] wave0_b;wire wave1_hs;wire wave1_vs;wire wave1_de;wire[7:0] wave1_r;wire[7:0] wave1_g;wire[7:0] wave1_b;wire adc_clk;wire adc0_buf_wr;wire[10:0] adc0_buf_addr;wire[7:0] adc0_bu
上傳時(shí)間： 2021-10-27
上傳用戶：qingfengchizhu
FPGA讀寫SD卡讀取BMP圖片通過(guò)LCD顯示例程實(shí)驗(yàn) Verilog邏輯源碼Quartus工程文件+文檔說(shuō)明,FPGA型號(hào)Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。1 實(shí)驗(yàn)簡(jiǎn)介在前面的實(shí)驗(yàn)中我們練習(xí)了 SD 卡讀寫，VGA 視頻顯示等例程，本實(shí)驗(yàn)將 SD 卡里的 BMP 圖片讀出，寫入到外部存儲(chǔ)器，再通過(guò) VGA、LCD 等顯示。本實(shí)驗(yàn)如果通過(guò)液晶屏顯示，需要有液晶屏模塊。2 實(shí)驗(yàn)原理在前面的實(shí)驗(yàn)中我們?cè)?VGA、LCD 上顯示的是彩條，是 FPGA 內(nèi)部產(chǎn)生的數(shù)據(jù)，本實(shí)驗(yàn)將彩條替換為 SD 內(nèi)的 BMP 圖片數(shù)據(jù)，但是 SD 卡讀取速度遠(yuǎn)遠(yuǎn)不能滿足顯示速度的要求，只能先寫入外部高速 RAM，再讀出后給視頻時(shí)序模塊顯示module top( input clk, input rst_n, input key1, output [5:0] seg_sel, output [7:0] seg_data, output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sd_ncs, //SD card chip select (SPI mode) output sd_dclk, //SD card clock output sd_mosi, //SD card controller data output input sd_miso, //SD card controller data input output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24
標(biāo)簽： fpga
上傳時(shí)間： 2021-10-27
上傳用戶：
Research on microwave power amplififiers has gained a growing importance demanded by the many continuously developing applications which require such subsystem performance. A broad set of commercial and strategic systems in fact have their overall performance boosted by the power amplififier, the latter becoming an enabling component wherever its effificiency and output power actually allows functionalities and operating modes previously not possible. This is the case for the many wireless systems and battery-operated systems that form the substrate of everyday life, but also of high-performance satellite and dual-use systems.
標(biāo)簽： 高效率 射頻 微波 固態(tài) 功率放大器
上傳時(shí)間： 2021-10-30
上傳用戶：得之我幸78
基于TMS320F2812 光伏并網(wǎng)發(fā)電模擬裝置PROTEL設(shè)計(jì)原理圖+PCB+軟件源碼+WORD論文文檔,硬件采用2層板設(shè)計(jì)，PROTEL99SE 設(shè)計(jì)的工程文件，包括完整的原理圖和PCB文件，可以做為你的學(xué)習(xí)設(shè)計(jì)參考。 摘要：本文實(shí)現(xiàn)了一個(gè)基于TMS320F2812 DSP芯片的光伏并網(wǎng)發(fā)電模擬裝置，采用直流穩(wěn)壓源和滑動(dòng)變阻器來(lái)模擬光伏電池。通過(guò)TMS320F2812 DSP芯片ADC模塊實(shí)時(shí)采樣模擬電網(wǎng)電壓的正弦參考信號(hào)、光伏電池輸出電壓、負(fù)載電壓電流反饋信號(hào)等。經(jīng)過(guò)數(shù)據(jù)處理后，用PWM模塊產(chǎn)生實(shí)時(shí)的SPWM 波，控制MOSFET逆變?nèi)珮蜉敵稣也ā１疚挠肞I控制算法實(shí)現(xiàn)了輸出信號(hào)對(duì)給定模擬電網(wǎng)電壓的正弦參考信號(hào)的頻率和相位跟蹤，用恒定電壓法實(shí)現(xiàn)了光伏電池最大功率點(diǎn)跟蹤（MPPT），從而達(dá)到模擬并網(wǎng)的效果。另外本裝置還實(shí)現(xiàn)了光伏電池輸出欠壓、負(fù)載過(guò)流保護(hù)功能以及光伏電池輸出欠壓、過(guò)流保護(hù)自恢復(fù)功能、聲光報(bào)警功能、孤島效應(yīng)的檢測(cè)、保護(hù)與自恢復(fù)功能。系統(tǒng)測(cè)試結(jié)果表明本設(shè)計(jì)完全滿定設(shè)計(jì)要求。關(guān)鍵詞：光伏并網(wǎng)，MPPT，DSP Photovoltaic Grid-connected generation simulator Zhangyuxin，Tantiancheng，Xiewuyang(College of Electrical Engineering, Chongqing University)Abstract: This paper presents a photovoltaic grid-connected generation simulator which is based on TMS320F2812 DSP, with a DC voltage source and a variable resistor to simulate the characteristic of photovoltaic cells. We use the internal AD converter to real-time sampling the referenced grid voltage signal, outputting voltage of photovoltaic, feedback outputting voltage and current signal. The PWM module generates SVPWM according to the calculation of the real-time sampling data, to control the full MOSFET inverter bridge output sine wave. We realized that the output voltage of the simulator can track the frequency and phase of the referenced grid voltage with PI regulation, and the maximum photovoltaic power tracking with constant voltage regulation, thereby achieved the purpose of grid-connected simulation. Additionally, this device has the over-voltage and over-current protection, audible and visual alarm, islanding detecting and protection, and it can recover automatically. The testing shows that our design is feasible.Keywords: Photovoltaic Grid-connected，MPPT，DSP 目錄引言 11. 方案論證 11.1. 總體介紹 11.2. 光伏電池模擬裝置 11.3. DC-AC逆變橋 11.4. MOSFET驅(qū)動(dòng)電路方案 21.5. 逆變電路的變頻控制方案 22. 理論分析與計(jì)算 22.1. SPWM產(chǎn)生 22.1.1. 規(guī)則采樣法 22.1.2. SPWM 脈沖的計(jì)算公式 32.1.3. SPWM 脈沖計(jì)算公式中的參數(shù)計(jì)算 32.1.4. TMS320F2812 DSP控制器的事件管理單元 42.1.5. 軟件設(shè)計(jì)方法 62.2. MPPT的控制方法與參數(shù)計(jì)算 72.3. 同頻、同相的控制方法和參數(shù)計(jì)算 8
標(biāo)簽： tms320f2812 光伏 并網(wǎng)發(fā)電 模擬 protel pcb
上傳時(shí)間： 2021-11-02
上傳用戶：
IIC接口E2PROM(AT24C64) 讀寫VERILOG 驅(qū)動(dòng)源碼+仿真激勵(lì)文件:module i2c_dri #( parameter SLAVE_ADDR = 7'b1010000 , //EEPROM從機(jī)地址 parameter CLK_FREQ = 26'd50_000_000, //模塊輸入的時(shí)鐘頻率 parameter I2C_FREQ = 18'd250_000 //IIC_SCL的時(shí)鐘頻率 ) ( input clk , input rst_n , //i2c interface input i2c_exec , //I2C觸發(fā)執(zhí)行信號(hào) input bit_ctrl , //字地址位控制(16b/8b) input i2c_rh_wl , //I2C讀寫控制信號(hào) input [15:0] i2c_addr , //I2C器件內(nèi)地址 input [ 7:0] i2c_data_w , //I2C要寫的數(shù)據(jù) output reg [ 7:0] i2c_data_r , //I2C讀出的數(shù)據(jù) output reg i2c_done , //I2C一次操作完成 output reg i2c_ack , //I2C應(yīng)答標(biāo)志 0:應(yīng)答 1:未應(yīng)答 output reg scl , //I2C的SCL時(shí)鐘信號(hào) inout sda , //I2C的SDA信號(hào) //user interface output reg dri_clk //驅(qū)動(dòng)I2C操作的驅(qū)動(dòng)時(shí)鐘 );//localparam definelocalparam st_idle = 8'b0000_0001; //空閑狀態(tài)localparam st_sladdr = 8'b0000_0010; //發(fā)送器件地址(slave address)localparam st_addr16 = 8'b0000_0100; //發(fā)送16位字地址localparam st_addr8 = 8'b0000_1000; //發(fā)送8位字地址localparam st_data_wr = 8'b0001_0000; //寫數(shù)據(jù)(8 bit)localparam st_addr_rd = 8'b0010_0000; //發(fā)送器件地址讀localparam st_data_rd = 8'b0100_0000; //讀數(shù)據(jù)(8 bit)localparam st_stop = 8'b1000_0000; //結(jié)束I2C操作//reg definereg sda_dir ; //I2C數(shù)據(jù)(SDA)方向控制reg sda_out ; //SDA輸出信號(hào)reg st_done ; //狀態(tài)結(jié)束reg wr_flag ; //寫標(biāo)志reg [ 6:0] cnt ; //計(jì)數(shù)reg [ 7:0] cur_state ; //狀態(tài)機(jī)當(dāng)前狀態(tài)reg [ 7:0] next_state; //狀態(tài)機(jī)下一狀態(tài)reg [15:0] addr_t ; //地址reg [ 7:0] data_r ; //讀取的數(shù)據(jù)reg [ 7:0] data_wr_t ; //I2C需寫的數(shù)據(jù)的臨時(shí)寄存reg [ 9:0] clk_cnt ; //分頻時(shí)
標(biāo)簽： iic 接口 e2prom at24c64 verilog 驅(qū)動(dòng) 仿真
上傳時(shí)間： 2021-11-05
上傳用戶：
FPGA讀取OV5640攝像頭數(shù)據(jù)并通過(guò)VGA或LCD屏顯示輸出的Verilog邏輯源碼Quartus工程文件+文檔說(shuō)明，F(xiàn)PGA型號(hào)Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, output cmos_scl, //cmos i2c clock inout cmos_sda, //cmos i2c data input cmos_vsync, //cmos vsync input cmos_href, //cmos hsync refrence,data valid input cmos_pclk, //cmos pxiel clock output cmos_xclk, //cmos externl clock input [7:0] cmos_db, //cmos data output cmos_rst_n, //cmos reset output cmos_pwdn, //cmos power down output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);
上傳時(shí)間： 2021-12-18
上傳用戶：
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