ARINC429總線協議是美國航空電子工程委員會(Airlines Engineering Committee)于1977年7月提出的，并于同年發表并獲得批準使用，它的全稱是數字式信息傳輸系統(Digital Information Transmission System ) 。協議標準規定了航空電子設備及有關系統間的數字信息傳輸要求。ARINC429廣泛應用在先進的民航客機中，如B-737、B-757、B-767，俄制軍用飛機也選用了類似的技術。 ARINC429總線結構簡單、性能穩定，抗干擾性強。最大的優勢在于可靠性高。飛機上的ARINC429數據總線，用于在系統和設備之間傳送上千種不同類型的參數，如航向、真空速、馬赫數等。
標簽： 429總線協議
上傳時間： 2016-08-17
上傳用戶：w50403
The AP2406 is a 1.5Mhz constant frequency, slope compensated current mode PWM step-down converter. The device integrates a main switch and a synchronous rectifier for high efficiency without an external Schottky diode. It is ideal for powering portable equipment that runs from a single cell lithium-Ion (Li+) battery. The AP2406 can supply 600mA of load current from a 2.5V to 5.5V input voltage. The output voltage can be regulated as low as 0.6V. The AP2406 can also run at 100% duty cycle for low dropout operation, extending battery life in portable system. Idle mode operation at light loads provides very low output ripple voltage for noise sensitive applications. The AP2406 is offered in a low profile (1mm) 5-pin, thin SOT package, and is available in an adjustable version and fixed output voltage of 1.2V, 1.5V and 1.8V
上傳時間： 2017-02-23
上傳用戶：w124141
題目：古典問題：有一對兔子，從出生后第3個月起每個月都生一對兔子，小兔子長到第三個月后每個月又生一對兔子，假如兔子都不死，問每個月的兔子總數為多少？ //這是一個菲波拉契數列問題 public class lianxi01 { public static void main(String[] args) { System.out.println("第1個月的兔子對數: 1"); System.out.println("第2個月的兔子對數: 1"); int f1 = 1, f2 = 1, f, M=24; for(int i=3; i<=M; i++) { f = f2; f2 = f1 + f2; f1 = f; System.out.println("第" + i +"個月的兔子對數: "+f2); } } } 【程序2】 題目：判斷101-200之間有多少個素數，并輸出所有素數。 程序分析：判斷素數的方法：用一個數分別去除2到sqrt(這個數)，如果能被整除， 則表明此數不是素數，反之是素數。 public class lianxi02 { public static void main(String[] args) { int count = 0; for(int i=101; i<200; i+=2) { boolean b = false; for(int j=2; j<=Math.sqrt(i); j++) { if(i % j == 0) { b = false; break; } else { b = true; } } if(b == true) {count ++;System.out.println(i );} } System.out.println( "素數個數是: " + count); } } 【程序3】 題目：打印出所有的 "水仙花數 "，所謂 "水仙花數 "是指一個三位數，其各位數字立方和等于該數本身。例如：153是一個 "水仙花數 "，因為153=1的三次方＋5的三次方＋3的三次方。 public class lianxi03 { public static void main(String[] args) { int b1, b2, b3;
上傳時間： 2017-12-24
上傳用戶：Ariza
基于FPGA設計的字符VGA LCD顯示實驗Verilog邏輯源碼Quartus工程文件+文檔說明,通過字符轉換工具將字符轉換為 8 進制 mif 文件存放到單端口的 ROM IP 核中，再從ROM 中把轉換后的數據讀取出來顯示到 VGA 上，FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue );wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;wire osd_hs;wire osd_vs;wire osd_de;wire[7:0] osd_r;wire[7:0] osd_g;wire[7:0] osd_b;assign vga_out_hs = osd_hs;assign vga_out_vs = osd_vs;assign vga_out_r = osd_r[7:3]; //discard low bit dataassign vga_out_g = osd_g[7:2]; //discard low bit dataassign vga_out_b = osd_b[7:3]; //discard low bit data//generate video pixel clockvideo_pll video_pll_m0( .inclk0 (clk ), .c0 (video_clk ));color_bar color_bar_m0( .clk (video_clk ), .rst (~rst_n ), .hs (video_hs ), .vs (video_vs ), .de (video_de ), .rgb_r (video_r ), .rgb_g (video_g ), .rgb_b (video_b ));osd_display osd_display_m0( .rst_n (rst_n ), .pclk (video_clk ), .i_hs (video_hs ), .i_vs (video_vs ), .i_de (video_de ), .i_data ({video_r,video_g,video_b} ), .o_hs (osd_hs ), .o_vs (osd_vs ), .o_de (osd_de ), .o_data ({osd_r,osd_g,osd_b} ));endmodule
上傳時間： 2021-12-18
上傳用戶：
基于FPGA設計的vga顯示測試實驗Verilog邏輯源碼Quartus工程文件+文檔說明，FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue );wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;assign vga_out_hs = video_hs;assign vga_out_vs = video_vs;assign vga_out_r = video_r[7:3]; //discard low bit dataassign vga_out_g = video_g[7:2]; //discard low bit dataassign vga_out_b = video_b[7:3]; //discard low bit data//generate video pixel clockvideo_pll video_pll_m0( .inclk0(clk), .c0(video_clk));color_bar color_bar_m0( .clk(video_clk), .rst(~rst_n), .hs(video_hs), .vs(video_vs), .de(video_de), .rgb_r(video_r), .rgb_g(video_g), .rgb_b(video_b));endmodule
標簽： fpga vga顯示 verilog quartus
上傳時間： 2021-12-19
上傳用戶：kingwide
FPGA Verilog HDL設計溫度傳感器ds18b20溫度讀取并通過lcd1620和8位LED數碼管顯示的QUARTUS II 12.0工程文件，包括完整的設計文件.V源碼，可以做為你的學習及設計參考。module ds18b20lcd1602display ( Clk, Rst, DQ, //18B20數據端口 Txd, //串口發送端口 LCD_Data, //lcd LCD_RS, LCD_RW, LCD_En, SMData, //數碼管段碼 SMCom //數碼管位碼 );input Rst,Clk;output Txd,LCD_RS,LCD_En,LCD_RW;inout DQ;output[7:0] LCD_Data;output[7:0] SMData;output[3:0] SMCom;wire DataReady;//測溫完成信號wire [15:0] MeasureResult;//DS18B20測溫結果reg [15:0] Temperature;//產生LCD的位碼和段碼LCD1602Display Gen_LCD(.resetin(Rst),.clkin(Clk),.Data16bIn(Temperature),.lcd_data(LCD_Data),.lcd_rs(LCD_RS),.lcd_rw(LCD_RW),.lcd_e(LCD_En)/*,.SMCom(SMCom)*/);//DS18B20測溫和發送 DS18B20 TmpMeasureAndTx(.Rst(Rst),.Clk(Clk),.DQ(DQ),.Txd(Txd),.FinishFlag(DataReady),.Data16b(MeasureResult));//產生數碼管的位碼和段碼SMDisplay Gen_SM(.Rst(Rst),.
標簽： fpga verilog hdl 溫度傳感器 ds18b20 lcd1620 數碼顯示
上傳時間： 2022-01-30
上傳用戶：
|- 數據科學速查表 - 0 B|- 遷移學習實戰 - 0 B|- 零起點Python機器學習快速入門 - 0 B|- 《深度學習入門：基于Python的理論與實現》高清中文版PDF+源代碼 - 0 B|- 《Python生物信息學數據管理》中文版PDF+英文版PDF+源代碼 - 0 B|- 《Python深度學習》2018中文版pdf+英文版pdf+源代碼 - 0 B|- 《Python編程：從入門到實踐》中文版+源代碼 - 0 B|- stanford machine learning - 0 B|- Python語言程序設計2018版電子教案 - 0 B|- Python網絡編程第三版 （原版+中文版+源代碼） - 0 B|- Python機器學習實踐指南（中文版帶書簽）、原書代碼、數據集 - 0 B|- python官方文檔 - 0 B|- Python編程(第4版 套裝上下冊) - 0 B|- PyQt5快速開發與實戰（pdf+源碼） - 0 B|- linux - 0 B|- 征服PYTHON-語言基礎與典型應用.pdf - 67.40 MB|- 與孩子一起學編程_中文版_詳細書簽.pdf - 69.10 MB|- 用Python做科學計算.pdf - 6.10 MB|- 用Python寫網絡爬蟲.pdf - 9.90 MB|- 用Python進行自然語言處理(中文翻譯NLTK).pdf - 4.40 MB|- 像計算機科學家那樣思考 Python中文版第二版.pdf - 712.00 kB|- 網絡爬蟲－Python和數據分析.pdf - 6.90 MB|- 圖解機器學習.pdf - 59.40 MB|- 凸優化.pdf - 5.70 MB|- 數據挖掘導論.pdf - 2.50 MB|- 數據科學入門.pdf - 13.30 MB|- 數據結構與算法__Python語言描述_裘宗燕編著_北京：機械工業出版社_，_2016.01_P346.pdf - 74.30 MB|- 神經網絡與深度學習.pdf - 92.60 MB|- 深入Python3...
標簽： python
上傳時間： 2022-06-06
上傳用戶：
數值分析高斯——列主元消去法主程序 說明如下： ％ a----input,matrix of coefficient ％ b----input,right vector ％ sol----output,returns the solution of linear equation
標簽： input coefficient matrix vector
上傳時間： 2017-01-01
上傳用戶：dancnc
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
上傳時間： 2013-10-23
上傳用戶：copu
design LP,HP,B S digital Butterworth and Chebyshev filter. All array has been specified internally,so user only need to input f1,f2,f3,f4,fs(in hz), alpha1,alpha2(in db) and iband (to specify the type of to design). This program output hk(z)=bk(z)/ak(z),k=1,2,..., ksection and the freq.
標簽： Butterworth internally Chebyshev specified
上傳時間： 2015-11-08
上傳用戶：253189838
