自己做的vhdl課程設計，交通燈：實現主干道倒計時，分別為30,20,5秒，分情況：當主干道有車時，紅黃綠交替，當只一個道路上有車時，那個道的交通燈變綠色，利用max+plus2做成，使用flex8000,epf8282alc84_4只用加一個38譯碼器模塊即可，使用別的板子也可以運行
標簽： vhdl
上傳時間： 2017-02-03
上傳用戶：努力努力再努力
c++語言程序設計超級簡單了解，你會驚喜地發現你可以后人乘涼：max是C++標準庫的一部分。
上傳時間： 2013-12-15
上傳用戶：啊颯颯大師的
Description The art galleries of the new and very futuristic building of the Center for Balkan Cooperation have the form of polygons (not necessarily convex). When a big exhibition is organized, watching over all of the pictures is a big security concern. Your task is that for a given gallery to write a program which finds the surface of the area of the floor, from which each point on the walls of the gallery is visible. On the figure 1. a map of a gallery is given in some co-ordinate system. The area wanted is shaded on the figure 2.
標簽： Description futuristic galleries the
上傳時間： 2017-02-17
上傳用戶：1427796291
Input : A set S of planar points Output : A convex hull for S Step 1: If S contains no more than five points, use exhaustive searching to find the convex hull and return. Step 2: Find a median line perpendicular to the X-axis which divides S into SL and SR SL lies to the left of SR . Step 3: Recursively construct convex hulls for SL and SR. Denote these convex hulls by Hull(SL) and Hull(SR) respectively. Step 4: Apply the merging procedure to merge Hull(SL) and Hull(SR) together to form a convex hull. Time complexity: T(n) = 2T(n/2) + O(n) = O(n log n)
標簽： contains Output convex planar
上傳時間： 2017-02-19
上傳用戶：wyc199288
Instead of finding the longest common subsequence, let us try to determine the length of the LCS. Then tracking back to find the LCS. Consider a1a2…am and b1b2…bn. Case 1: am=bn. The LCS must contain am, we have to find the LCS of a1a2…am-1 and b1b2…bn-1. Case 2: am≠bn. Wehave to find the LCS of a1a2…am-1 and b1b2…bn, and a1a2…am and b b b b1b2…bn-1 Let A = a1 a2 … am and B = b1 b2 … bn Let Li j denote the length of the longest i,g g common subsequence of a1 a2 … ai and b1 b2 … bj. Li,j = Li-1,j-1 + 1 if ai=bj max{ L L } a≠b i-1,j, i,j-1 if ai≠j L0,0 = L0,j = Li,0 = 0 for 1≤i≤m, 1≤j≤n.
標簽： the subsequence determine Instead
上傳時間： 2013-12-17
上傳用戶：evil
4位電子智能密碼鎖，基于VHDL語言設計，MAX+PLUSⅡ環境下實現
上傳時間： 2013-11-30
上傳用戶：athjac
1. socket通信：有客戶端和服務端的socket代碼。 2. 多線程：客戶端和服務端各用一線程發送信息；服務端另有一監聽線程，用于把超時的信息刪除。 這里應用到了同步，使兩個線程可以操作同一個map。
上傳時間： 2017-02-27
上傳用戶：lanwei
cordic methods describe essentially the same algorithm that with suitably chosen inputs can be used to calculate a whole range of scientific functions including sin, cos, tan, arctan, arcsin, arccos, sinh, cosh, tanh, arctanh, log, exp, square root and even multiply and divide. the method dates back to volder [1959], and due to its versatility and compactness, it made possible the microcoding of the hp35 pocket scientific calculator in 1972. here is some code to illustrate the techniques. ive split the methods into three parts linear, circular and hyperbolic. in the hp35 microcode these would be unified into one function (for space reasons). because the linear mode can perform multiply and divide, you only need add/subtract and shift to complete the implementation. you can select in the code whether to do the multiples and divides also by cordic means. other multiplies and divides are all powers of 2 (these dont count). to eliminate these too, would involve ieee hackery.
標簽： essentially algorithm describe suitably
上傳時間： 2017-03-02
上傳用戶：litianchu
Verilog HDL的程式，上網找到SPI程式， vspi.v這程式相當好用可用來接收與傳送SPI，並且寫了一個傳輸信號測試，spidatasent.v這程式就是傳送的資料，分別為00 66... 01 77...... 02 55這樣的資料，並透過MAX+PULS II軟體進行模擬，而最外層的程式是test_createspi.v！
上傳時間： 2017-03-06
上傳用戶：onewq
Verilog是廣泛應用的硬件描述語言，可以用在硬件設計流程的建模、綜合和模擬等多個階段。隨著硬件設計規模的不斷擴大，應用硬件描述語言進行描述的CPLD結構，成為設計專用集成電路和其他集成電路的主流。通過應用Verilog HDL對多功能電子鐘的設計，達到對Verilog HDL的理解，同時對CPLD器件進行簡要了解。 本文的研究內容包括: 對Altera公司Flex 10K系列的EPF10K 10簡要介紹，Altera公司軟件Max+plusⅡ簡要介紹和應用Verilog HDL對多功能電子鐘進行設計。
上傳時間： 2017-03-06
上傳用戶：epson850
