This document describes how to switch to and program the unisersal serial bus (USB) analog phase-Locked loop (APLL) on the C5506/C5507/C5509A devices. Example assembly programs for programming and switching to and from the APLL are also provided in the attached zip file. It is assumed that the reader is familiar with the use and operation of the C5506/C5507/C5509A USB digital phase-Locked loop (DPLL) and C55x™ Digital Signal Processor (DSP) IDLE procedures.
標簽： describes unisersal document phase-lo
上傳時間： 2014-01-13
上傳用戶：hustfanenze
The Hilbert Transform is an important component in communication systems, e.g. for single sideband modulation/demodulation, amplitude and phase detection, etc. It can be formulated as filtering operation which makes it possible to approximate the Hilbert Transform with a digital filter. Due to the non-causal and infinite impulse response of that filter, it is not that easy to get a good approximation with low hardware resource usage. Therefore, different filters with different complexities have been implemented. The detailed discussion can be found in "Digital Hilbert Transformers or FPGA-based Phase-Locked Loops" (http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4629940). The design is fully pipelined for maximum throughput.
標簽： e.g. communication Transform important
上傳時間： 2017-06-25
上傳用戶：gxf2016
What happens with your machine when you need to move away from the computer for 10 or more minutes? How secure is your data? Can someone sit on your chair while you are at a coworkers office and play with your data? Maybe you need a computer locking tool that is small and easy to use yet powerful enough to make sure your machine is Locked when you need to go out for a break.
標簽： computer happens machine minutes
上傳時間： 2017-08-24
上傳用戶：semi1981
描述 了PLL 的基礎知識哦，非常的 實用
標簽： Phase Locked Loop Design Fundamentals
上傳時間： 2017-03-13
上傳用戶：rfzhangyicheng
PLL(Phase Locked Loop)： 為鎖相回路或鎖相環，用來統一整合時鐘信號，使高頻器件正常工作，如內存的存取資料等。PLL用于振蕩器中的反饋技術。 許多電子設備要正常工作，通常需要外部的輸入信號與內部的振蕩信號同步。一般的晶振由于工藝與成本原因，做不到很高的頻率，而在需要高頻應用時，由相應的器件VCO，實現轉成高頻，但并不穩定，故利用鎖相環路就可以實現穩定且高頻的時鐘信號。
上傳時間： 2021-07-23
上傳用戶：紫陽帝尊
ADC模數轉換器件Altium Designer AD原理圖庫元件庫SV text has been written to file : 4.4 - ADC模數轉換器件.csvLibrary Component Count : 29Name Description----------------------------------------------------------------------------------------------------ADC0800 National 8-Bit Analog to Digital ConverterADC0809 ADC0831 ADCADC0832 ADC8 Generic 8-Bit A/D ConverterCLC532 High-Speed 2:1 Analog MultiplexerCS5511 National 16-Bit Analog to Digital ConverterDAC8 Generic 8-Bit D/A ConverterEL1501 Differential line Driver/ReceiverEL2082 Current-Mode MultiplierEL4083 Current Mode Four Quadrant MultiplierEL4089 DC Restored Video AmplifierEL4094 Video Gain Control/FaderEL4095 Video Gain Contol/Fader/MultiplexerICL7106 LMC6953_NSC PCI Local Bus Power SupervisorMAX4147 300MHz, Low-Power, High-Output-Current, Differential Line DriverMAX4158 350MHz 2-Channel Video Multiplexer-AmplifierMAX4159 350MHz 2-Channel Video Multiplexer-AmplifierMAX4258 250MHz, 2-Channel Video Multiplexer-AmplifierMAX4259 250MHz 2-Channel Video Multiplexer-AmplifierMAX951 Ultra-Low-Power, Single-Supply Op Amp + Comparator + ReferenceMAX952 Ultra-Low-Power, Single-Supply Op Amp + Comparator + ReferenceMC1496 Balanced Modulator/DemodulatorPLL100k Generic Phase Locked LoopPLL10k Generic Phase Locked LoopPLL5k Generic Phase Locked LoopPLLx Generic Phase Locked Loop水位計
標簽： adc 模數轉換 altium designer
上傳時間： 2022-03-13
上傳用戶：
Abstract: A sliding mode observer and fractional-order phase-Locked loop (FO-PLL) method is proposed for the sensorless speed control of a permanent magnet synchronous motor (PMSM).The saturation function is adopted in order to reduce the chattering phenomenon caused by the sliding mode observer. In this proposed FO-PLL, method, a regulable fractional order r is involved, which means that the FO-PLL provides an extra degree of freedom. In fact, the conventional phase-Locked loop (PLL) applied in sensorless PMSM control can be seen as a special case of the proposed FO-PLL. By selecting a proper fractional order r a better performance may be achieved. The computer simulation results demonstrate the effectiveness of the proposed method.Key words: fractional calculus; fractional order phase-Locked loop; sensorless control; sliding mode observer; permanent magnet synchronous motor; speed controll
上傳時間： 2022-06-18
上傳用戶：
一.基礎理論鎖相環路（Phase Locked Loop）是一個閉環的相位控制系統，它的輸出信號的相位能自動跟蹤輸入信號相位。系統框圖如下：當0，（1）與0：（1）相等時，兩矢量以相同的角速度旋轉，相對位置，即夾角維持不變，通常數值又較小，這就是環路的鎖定狀態。從輸入信號加到鎖相環路的輸入端開始，一直到環路達到鎖定的全過程，稱為捕獲過程。設系統最初進入同步狀態[2nrtto，e，.]的時間為1。。那么從1=1，的起始狀態到達進入同步狀態的全部過程就稱為鎖相環路的捕獲過程。捕獲過程所需的時間T，=1，-1，稱為捕獲時間。顯然，捕獲時間T，的大小不但與環路的參數有關，而且與起始狀態有關。對一定的環路來說，是否能通過捕獲而進入同步完全取決于起始頻差8.（4）-Ao。。若Ao，超過某一范圍，環路就不能捕獲了。這個范圍的大小是鎖相環路的一個重要性能指標，稱為環路的捕獲帶Ao，。
標簽： 射頻鎖相環
上傳時間： 2022-06-21
上傳用戶：
