Hyperlynx仿真應(yīng)用:阻抗匹配.下面以一個(gè)電路設(shè)計(jì)為例，簡(jiǎn)單介紹一下PCB仿真軟件在設(shè)計(jì)中的使用。下面是一個(gè)DSP硬件電路部分元件位置關(guān)系(原理圖和PCB使用PROTEL99SE設(shè)計(jì))，其中DRAM作為DSP的擴(kuò)展Memory(64位寬度，低8bit還經(jīng)過(guò)3245接到FLASH和其它芯片)，DRAM時(shí)鐘頻率133M。因?yàn)轭l率較高，設(shè)計(jì)過(guò)程中我們需要考慮DRAM的數(shù)據(jù)、地址和控制線是否需加串阻。下面，我們以數(shù)據(jù)線D0仿真為例看是否需要加串阻。模型建立首先需要在元件公司網(wǎng)站下載各器件IBIS模型。然后打開(kāi)Hyperlynx,新建LineSim File(線路仿真—主要用于PCB前仿真驗(yàn)證)新建好的線路仿真文件里可以看到一些虛線勾出的傳輸線、芯片腳、始端串阻和上下拉終端匹配電阻等。下面，我們開(kāi)始導(dǎo)入主芯片DSP的數(shù)據(jù)線D0腳模型。左鍵點(diǎn)芯片管腳處的標(biāo)志，出現(xiàn)未知管腳，然后再按下圖的紅線所示線路選取芯片IBIS模型中的對(duì)應(yīng)管腳。 3http://bbs.elecfans.com/ 電子技術(shù)論壇 http://www.elecfans.com 電子發(fā)燒友點(diǎn)OK后退到“ASSIGN Models”界面。選管腳為“Output”類型。這樣，一樣管腳的配置就完成了。同樣將DRAM的數(shù)據(jù)線對(duì)應(yīng)管腳和3245的對(duì)應(yīng)管腳IBIS模型加上(DSP輸出，3245高阻，DRAM輸入)。下面我們開(kāi)始建立傳輸線模型。左鍵點(diǎn)DSP芯片腳相連的傳輸線，增添傳輸線，然后右鍵編輯屬性。因?yàn)槲覀兪褂盟膶影澹诒韺幼呔€，所以要選用“Microstrip”，然后點(diǎn)“Value”進(jìn)行屬性編輯。這里，我們要編輯一些PCB的屬性，布線長(zhǎng)度、寬度和層間距等，屬性編輯界面如下：再將其它傳輸線也添加上。這就是沒(méi)有加阻抗匹配的仿真模型(PCB最遠(yuǎn)直線間距1.4inch，對(duì)線長(zhǎng)為1.7inch)。現(xiàn)在模型就建立好了。仿真及分析下面我們就要為各點(diǎn)加示波器探頭了，按照下圖紅線所示路徑為各測(cè)試點(diǎn)增加探頭：為發(fā)現(xiàn)更多的信息，我們使用眼圖觀察。因?yàn)闀r(shí)鐘是133M，數(shù)據(jù)單沿采樣，數(shù)據(jù)翻轉(zhuǎn)最高頻率為66.7M，對(duì)應(yīng)位寬為7.58ns。所以設(shè)置參數(shù)如下：之后按照芯片手冊(cè)制作眼圖模板。因?yàn)槲覀冏铌P(guān)心的是接收端(DRAM)信號(hào)，所以模板也按照DRAM芯片HY57V283220手冊(cè)的輸入需求設(shè)計(jì)。芯片手冊(cè)中要求輸入高電平VIH高于2.0V，輸入低電平VIL低于0.8V。DRAM芯片的一個(gè)NOTE里指出，芯片可以承受最高5.6V，最低-2.0V信號(hào)(不長(zhǎng)于3ns)：按下邊紅線路徑配置眼圖模板：低8位數(shù)據(jù)線沒(méi)有串阻可以滿足設(shè)計(jì)要求，而其他的56位都是一對(duì)一，經(jīng)過(guò)仿真沒(méi)有串阻也能通過(guò)。于是數(shù)據(jù)線不加串阻可以滿足設(shè)計(jì)要求，但有一點(diǎn)需注意，就是寫數(shù)據(jù)時(shí)因?yàn)榇嬖诨貨_，DRAM接收高電平在位中間會(huì)回沖到2V。因此會(huì)導(dǎo)致電平判決裕量較小，抗干擾能力差一些，如果調(diào)試過(guò)程中發(fā)現(xiàn)寫RAM會(huì)出錯(cuò)，還需要改版加串阻。
上傳時(shí)間： 2013-12-17
上傳用戶：debuchangshi
Explain how to open the Waveform Viewer for Verification ? State how to insert nodes into the Waveform Viewer ? Tell how to ASSIGN Stimulus with the Stimulator Selector
標(biāo)簽： Foundation 仿真
上傳時(shí)間： 2013-10-29
上傳用戶：daguogai
It may analyze the window structure, the advancement and the window news, has the very greatly auxiliary function to the development work. When we need to study some object, so long as ASSIGNs out its search window, drives the detector the indicator to ASSIGN the window/to control on to release then. Under, the author on and everybody same place, makes with VC to belong to own Spy++.
標(biāo)簽： the window advancement structure
上傳時(shí)間： 2013-12-31
上傳用戶：ghostparker
How the K-mean Cluster work Step 1. Begin with a decision the value of k = number of clusters Step 2. Put any initial partition that classifies the data into k clusters. You may ASSIGN the training samples randomly, or systematically as the following: Take the first k training sample as single-element clusters ASSIGN each of the remaining (N-k) training sample to the cluster with the nearest centroid. After each ASSIGNment, recomputed the centroid of the gaining cluster. Step 3 . Take each sample in sequence and compute its distance from the centroid of each of the clusters. If a sample is not currently in the cluster with the closest centroid, switch this sample to that cluster and update the centroid of the cluster gaining the new sample and the cluster losing the sample. Step 4 . Repeat step 3 until convergence is achieved, that is until a pass through the training sample causes no new ASSIGNments.
標(biāo)簽： the decision clusters Cluster
上傳時(shí)間： 2013-12-21
上傳用戶：gxmm
表達(dá)式類型的實(shí)現(xiàn): 1、 一個(gè)表達(dá)式和一顆二叉樹(shù)之間，存在著自然的對(duì)應(yīng)關(guān)系。 2、 假設(shè)算術(shù)表達(dá)式Expression內(nèi)可以含有變量（a～z）、常量（0～9）和二元運(yùn)算符（＋，－，*，/，^）。實(shí)現(xiàn)一下操作。 （1） ReadExpr(E)——以字符序列的形式輸入語(yǔ)法正確的前綴表示式并構(gòu)造表達(dá)式E。 （2） WritrExpr(E)——用帶括弧的中綴表示式輸出表達(dá)式E。 （3） ASSIGN(V,c)——實(shí)現(xiàn)對(duì)變量V的賦值(V=c),變量的初值為0。 （4） Value(E)——對(duì)算術(shù)表達(dá)式E求值。 （5） CompoundExpr(P,E1,E2)——構(gòu)造一個(gè)新的復(fù)合表達(dá)式（E1）P (E2)。
上傳時(shí)間： 2013-12-09
上傳用戶：luke5347
1．一個(gè)表達(dá)式和一個(gè)二叉樹(shù)之間，存在著自然的對(duì)應(yīng)關(guān)系。寫一個(gè)程序，實(shí)現(xiàn)基于二叉樹(shù)表示的算術(shù)表達(dá)式Expression的操作。 2．假設(shè)算術(shù)表達(dá)式Expression內(nèi)可以含有變量（a~z）、常量（0~9）和二元運(yùn)算符（+，-，*，/，^(乘冪)）。實(shí)現(xiàn)以下操作： ⑴ReadExpr（E）——以字符序列的形式輸入語(yǔ)法正確的前綴表達(dá)式并構(gòu)造表達(dá)式E。 ⑵WriteExpr（E）——用帶括弧的中綴表達(dá)式輸出表達(dá)式E。 ⑶ASSIGN（V，c）——實(shí)現(xiàn)對(duì)變量Vde賦值（V=c），變量的初值為0。 ⑷Value（E）——對(duì)算術(shù)表達(dá)式E求值。 ⑸CompoundExpr（P，E1，E2）——構(gòu)造一個(gè)新的復(fù)合表達(dá)式（E1）P（E2）。 3．在讀入表達(dá)的字符序列的同時(shí)，完成運(yùn)算符和運(yùn)算數(shù)的識(shí)別和處理以及相應(yīng)的運(yùn)算。 4．在識(shí)別出運(yùn)算數(shù)的同時(shí)，要將其字符形式轉(zhuǎn)換成整數(shù)形式。 5．用在后根遍歷的次序?qū)Ρ磉_(dá)式求值。
上傳時(shí)間： 2014-11-27
上傳用戶：偷心的海盜
夏宇聞8位RISC_CPU的完整代碼+TESTBENCH（已調(diào)試） modelsim工程文件，包括書(shū)中所測(cè)試的三個(gè)程序和相關(guān)數(shù)據(jù)，絕對(duì)可用~所有信號(hào)名均遵從原書(shū)。在論壇中沒(méi)有找到testbench的，只有一個(gè)mcu的代碼，但很多和書(shū)中的是不一樣的，自己改了下下~`````大家多多支持啊~`我覺(jué)得書(shū)中也還是有些不盡如人意的地方，如clk_gen.v中clk2,clk4是沒(méi)有用的，ASSIGN clk1=~clk再用clk1的negedge clk1來(lái)觸發(fā)各個(gè)module也是不太好的，會(huì)使時(shí)序惡化，綜合時(shí)很可能會(huì)setup vio的，所以覺(jué)得直接用clk的上升沿來(lái)觸發(fā)各個(gè)module比較好
標(biāo)簽： TESTBENCH RISC_CPU modelsim 8位
上傳時(shí)間： 2014-01-08
上傳用戶：ippler8
Airline Reservations System A small airline has just purchased a computer for its new automated reservation system. You have been asked to develop the new system called ARSystem. You are to write an application to ASSIGN seats on each flight of the airline s only plane (capacity: 24 seats.) Your application should display the following alternatives: Please type 1 for FirstClass and Please type 2 for Economy. If the user types 1, your application should ASSIGN a seat in the first-class section (seats 1-8). If the user types 2, your application should ASSIGN a seat in the economy section (seats 9-24). Your application should then display a boarding pass indicating the person s seat number and whether it is in the first-class or economy
標(biāo)簽： Reservations automated purchased computer
上傳時(shí)間： 2017-04-14
上傳用戶：lizhizheng88
In this paper we present a classifier called bi-density twin support vector machines (BDTWSVMs) for data classification. In the training stage, BDTWSVMs first compute the relative density degrees for all training points using the intra-class graph whose weights are determined by a local scaling heuristic strategy, then optimize a pair of nonparallel hyperplanes through two smaller sized support vector machine (SVM)-typed problems. In the prediction stage, BDTWSVMs ASSIGN to the class label depending on the kernel density degree-based distances from each test point to the two hyperplanes. BDTWSVMs not only inherit good properties from twin support vector machines (TWSVMs) but also give good description for data points. The experimental results on toy as well as publicly available datasets indicate that BDTWSVMs compare favorably with classical SVMs and TWSVMs in terms of generalization
標(biāo)簽： recognition Bi-density machines support pattern vector twin for
上傳時(shí)間： 2019-06-09
上傳用戶：lyaiqing
基于FPGA設(shè)計(jì)的字符VGA LCD顯示實(shí)驗(yàn)Verilog邏輯源碼Quartus工程文件+文檔說(shuō)明,通過(guò)字符轉(zhuǎn)換工具將字符轉(zhuǎn)換為 8 進(jìn)制 mif 文件存放到單端口的 ROM IP 核中，再?gòu)腞OM 中把轉(zhuǎn)換后的數(shù)據(jù)讀取出來(lái)顯示到 VGA 上，F(xiàn)PGA型號(hào)Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue );wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;wire osd_hs;wire osd_vs;wire osd_de;wire[7:0] osd_r;wire[7:0] osd_g;wire[7:0] osd_b;ASSIGN vga_out_hs = osd_hs;ASSIGN vga_out_vs = osd_vs;ASSIGN vga_out_r = osd_r[7:3]; //discard low bit dataASSIGN vga_out_g = osd_g[7:2]; //discard low bit dataASSIGN vga_out_b = osd_b[7:3]; //discard low bit data//generate video pixel clockvideo_pll video_pll_m0( .inclk0 (clk ), .c0 (video_clk ));color_bar color_bar_m0( .clk (video_clk ), .rst (~rst_n ), .hs (video_hs ), .vs (video_vs ), .de (video_de ), .rgb_r (video_r ), .rgb_g (video_g ), .rgb_b (video_b ));osd_display osd_display_m0( .rst_n (rst_n ), .pclk (video_clk ), .i_hs (video_hs ), .i_vs (video_vs ), .i_de (video_de ), .i_data ({video_r,video_g,video_b} ), .o_hs (osd_hs ), .o_vs (osd_vs ), .o_de (osd_de ), .o_data ({osd_r,osd_g,osd_b} ));endmodule
上傳時(shí)間： 2021-12-18
上傳用戶：
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