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• an up down counter in verilog免費下載

  資源簡介：an up down counter in verilog

  標簽： counter verilog down an

  上傳時間： 2014-01-24

  上傳用戶：趙云興

• an up down counter for AVR免費下載

  資源簡介：an up down counter for AVR

  標簽： counter down AVR for

  上傳時間： 2014-01-05

  上傳用戶：youth25

• Up down counter for microchip ASM code tested免費下載

  資源簡介：Up down counter for microchip ASM code tested

  標簽： microchip counter tested down

  上傳時間： 2013-12-17

  上傳用戶：xieguodong1234

• Up-down Asynchronous counter in Behavioral Model免費下載

  資源簡介：Up-down Asynchronous counter in Behavioral Model

  標簽： Asynchronous Behavioral Up-down counter

  上傳時間： 2017-05-21

  上傳用戶：caozhizhi

• This book is for you if You re no "dummy," and you need to get quickly up to speed in intermediate免費下載

  資源簡介：This book is for you if You re no "dummy," and you need to get quickly up to speed in intermediate to advanced C++ You ve had some experience in C++ programming, but reading intermediate and advanced C++ books is slow-going You ve had an...

  標簽： intermediate you quickly dummy

  上傳時間： 2014-01-09

  上傳用戶：wpwpwlxwlx

• The purpose of this chapter is to bring relative newcomers up to speed in writing, compiling, and pa免費下載

  資源簡介：The purpose of this chapter is to bring relative newcomers up to speed in writing, compiling, and packaging servlets and JSPs. If you have never developed a servlet or JSP before, or just need to brush up on the technology to jumpstart your...

  標簽： compiling newcomers relative purpose

  上傳時間： 2014-01-13

  上傳用戶：541657925

• mining source code written in verilog免費下載

  資源簡介：mining source code written in verilog

  標簽： verilog written mining source

  上傳時間： 2015-05-06

  上傳用戶：asddsd

• MSP-FET430P140 Demo - Timer_B, PWM TB1-2, Up/down Mode, DCO SMCLK免費下載

  資源簡介：MSP-FET430P140 Demo - Timer_B, PWM TB1-2, Up/down Mode, DCO SMCLK

  標簽： MSP-FET Timer_B SMCLK Demo

  上傳時間： 2015-10-10

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• mips prcessor in verilog and vhdl免費下載

  資源簡介：mips prcessor in verilog and vhdl

  標簽： prcessor verilog mips vhdl

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• Every day, patches are created to cover up security holes in software applications and operating sys免費下載

  資源簡介：Every day, patches are created to cover up security holes in software applications and operating systems. But by the time you download a patch, it could be too late. A hacker may have already taken advantage of the hole and wreaked havoc on...

  標簽： applications operating security software

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• j2me方向的控制的演示,手機上的up,down,left,right等的控制的和顯示免費下載

  資源簡介：j2me方向的控制的演示,手機上的up,down,left,right等的控制的和顯示

  標簽： right j2me down left

  上傳時間： 2013-11-26

  上傳用戶：牛津鞋

• Generic FIFO, writen in verilog hdl免費下載

  資源簡介：Generic FIFO, writen in verilog hdl

  標簽： Generic verilog writen FIFO

  上傳時間： 2016-02-18

  上傳用戶：zwei41

• TxQuery is an SQL engine implemented in a TDataSet descendant component, that can parse SQL syntax,免費下載

  資源簡介：TxQuery is an SQL engine implemented in a TDataSet descendant component, that can parse SQL syntax, and that will use that syntax to query to another.

  標簽： implemented descendant SQL component

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• an instant messenger written in java (client)免費下載

  資源簡介：an instant messenger written in java (client)

  標簽： messenger instant written client

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• As the source code name, this code is writing in verilog and also inside the folder there is a c cod免費下載

  資源簡介：As the source code name, this code is writing in verilog and also inside the folder there is a c code to see the simulation results from verilog.

  標簽： code the verilog writing

  上傳時間： 2013-12-27

  上傳用戶：wangdean1101

• ST32 基于（英蓓特）STM32V100的EXTI程序 This example shows how to configure an external interrupt line. In t免費下載

  資源簡介：ST32 基于（英蓓特）STM32V100的EXTI程序 This example shows how to configure an external interrupt line. In this example, the EXTI line 9 is configured to generate an interrupt on each falling edge. In the interrupt routine a led connecte...

  標簽： configure interrupt external example

  上傳時間： 2016-11-17

  上傳用戶：GavinNeko

• Writing Testbenches classic book in verilog testbench免費下載

  資源簡介：Writing Testbenches classic book in verilog testbench

  標簽： Testbenches testbench Writing classic

  上傳時間： 2014-08-03

  上傳用戶：ddddddos

• This is GMS down upper converter and down converter in simulink. you may understand the structure in免費下載

  資源簡介：This is GMS down upper converter and down converter in simulink. you may understand the structure in here, believe is useful to those who interested in telecommunication

  標簽： converter down understand structure

  上傳時間： 2017-03-04

  上傳用戶：朗朗乾坤

• Color space converter in verilog HDL免費下載

  資源簡介：Color space converter in verilog HDL

  標簽： converter verilog Color space

  上傳時間： 2013-12-22

  上傳用戶：Late_Li

• JPEG encoder in verilog免費下載

  資源簡介：JPEG encoder in verilog

  標簽： encoder verilog JPEG in

  上傳時間： 2013-12-31

  上傳用戶：龍飛艇

• pll in verilog in the Appendix免費下載

  資源簡介：pll in verilog in the Appendix

  標簽： Appendix verilog in pll

  上傳時間： 2017-03-24

  上傳用戶：集美慧

• an electronic diary programmed in java免費下載

  資源簡介：an electronic diary programmed in java

  標簽： electronic programmed diary java

  上傳時間： 2017-03-28

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• xmodem.tar.gz Linux X-Modem Up/down Client Source免費下載

  資源簡介：xmodem.tar.gz Linux X-Modem Up/down Client Source

  標簽： X-Modem xmodem Client Source

  上傳時間： 2017-04-03

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• Code for top down parser in C++免費下載

  資源簡介：Code for top down parser in C++

  標簽： parser Code down for

  上傳時間： 2014-01-16

  上傳用戶：lhw888

• This is a simple MIPS processor datapath written in verilog hardware language. You can see the signa免費下載

  資源簡介：This is a simple MIPS processor datapath written in verilog hardware language. You can see the signals when emulating in signalscan. Compile it with verilog in linux.

  標簽： processor datapath hardware language

  上傳時間： 2017-04-22

  上傳用戶：磊子226

• Booth multiplier written in verilog免費下載

  資源簡介：Booth multiplier written in verilog

  標簽： multiplier written verilog Booth

  上傳時間： 2017-04-22

  上傳用戶：天涯

• This example sets up the PLL in x10/2 mode, divides SYSCLKOUT by six to reach a 25Mhz HSPCLK (assumi免費下載

  資源簡介：This example sets up the PLL in x10/2 mode, divides SYSCLKOUT by six to reach a 25Mhz HSPCLK (assuming a 30Mhz XCLKIN). The clock divider in the ADC is not used so that the ADC will see the 25Mhz on the HSPCLK. Interrupts are enabled and ...

  標簽： SYSCLKOUT example divides HSPCLK

  上傳時間： 2014-01-25

  上傳用戶：ljt101007

• 6 bit wallace reduction in verilog免費下載

  資源簡介：6 bit wallace reduction in verilog

  標簽： reduction wallace verilog bit

  上傳時間： 2017-04-25

  上傳用戶：bcjtao

• an implementation of Notch_Filter in matlab for image processing免費下載

  資源簡介：an implementation of Notch_Filter in matlab for image processing

  標簽： implementation Notch_Filter processing matlab

  上傳時間： 2017-04-30

  上傳用戶：kernaling

• introduction to combinational logic in verilog免費下載

  資源簡介：introduction to combinational logic in verilog

  標簽： combinational introduction verilog logic

  上傳時間： 2014-01-08

  上傳用戶：363186