My thesis entitled "fpga digital clock," immature, to enlighten
資源簡(jiǎn)介：My thesis entitled "fpga digital clock," immature, to enlighten
上傳時(shí)間： 2014-01-02
上傳用戶：hxy200501
資源簡(jiǎn)介：My thesis entitled \"fpga digital clock,\" immature, to enlighten
上傳時(shí)間： 2013-08-31
上傳用戶：smallfish
資源簡(jiǎn)介：This set of files contains my Thesis work on cdma modem. Just extract the files to use them
上傳時(shí)間： 2013-12-17
上傳用戶：ljmwh2000
資源簡(jiǎn)介：This code was used for making the practical measurements in section 2.3 of my thesis. This Matlab code allows an OFDM signal to be generated based on an input data file. The data can be random data, a grey scale image, a wave file, or any t...
上傳時(shí)間： 2015-09-20
上傳用戶：tedo811
資源簡(jiǎn)介：This is the source code of a digital clock implemented using Atmel 8 bit AVR Controller(ATMega16). To fully understand it look at the hardware implementation shown in attached photo(pdf).
上傳時(shí)間： 2014-08-18
上傳用戶：moshushi0009
資源簡(jiǎn)介：good morning,my dear teachers,my dear professors.i am very glad to be here for your interview.my name is song yonghao,i am 22 years old .i come from luoyang,a very beautiful aicent city.my undergratuade period will be accomplished in changa...
上傳時(shí)間： 2015-05-24
上傳用戶：shus521
資源簡(jiǎn)介：digital Clock in Assembly 我的一個(gè)大學(xué)滿分VHDL作品，數(shù)字石英鐘的模擬程序。
上傳時(shí)間： 2014-01-25
上傳用戶：hullow
資源簡(jiǎn)介：digital CLOCK！看了就知道了！很不錯(cuò)的東西！可以幫助你省下不少精力！
上傳時(shí)間： 2014-11-08
上傳用戶：dbs012280
資源簡(jiǎn)介：it is a digital clock
上傳時(shí)間： 2015-12-18
上傳用戶：teddysha
資源簡(jiǎn)介：digital Clock Source using ATmega8515 and 7Segment
上傳時(shí)間： 2014-01-24
上傳用戶：王慶才
資源簡(jiǎn)介：This document gives a project with title digital clock using labview.
上傳時(shí)間： 2017-03-20
上傳用戶：風(fēng)之驕子
資源簡(jiǎn)介：many application on kit SP-3: VGA, digital clock, counter, interface PS2....
上傳時(shí)間： 2017-04-17
上傳用戶：talenthn
資源簡(jiǎn)介：use grapcic Dos C pain digital clock
上傳時(shí)間： 2017-06-09
上傳用戶：xymbian
資源簡(jiǎn)介：digital clock and thermometer pic16f84
上傳時(shí)間： 2014-01-24
上傳用戶：skfreeman
資源簡(jiǎn)介：digital clock using 8051 timer for atmel at89c52 or At89s52
上傳時(shí)間： 2017-07-16
上傳用戶：xymbian
資源簡(jiǎn)介：digital clock arm sample code using for beginer
上傳時(shí)間： 2017-07-19
上傳用戶：邶刖
資源簡(jiǎn)介：Programm that represents digital clock
上傳時(shí)間： 2013-12-31
上傳用戶：liglechongchong
資源簡(jiǎn)介：digital CLock Upload!
上傳時(shí)間： 2017-08-19
上傳用戶：小鵬
資源簡(jiǎn)介：Java Clock is a FREE Java applet used to display a clock on your Web pages. You can display either analog or digital clock. The full source code of this applet is also available (visit my home page to download it). You may use this applet o...
上傳時(shí)間： 2014-01-12
上傳用戶：woshiayin
資源簡(jiǎn)介：As businesses and consumers expect more fromportable electronics, the FPGA industry has beencompelled to re-think how it serves these low-power,cost-sensitive markets. Application classes like
上傳時(shí)間： 2013-11-10
上傳用戶：XLHrest
資源簡(jiǎn)介：本文利用Verilog HDL 語言自頂向下的設(shè)計(jì)方法設(shè)計(jì)多功能數(shù)字鐘，突出了其作為硬件描述語言的良好的可讀性、可移植性和易理解等優(yōu)點(diǎn)，并通過Altera QuartusⅡ 4.1 和ModelSim SE 6.0 完成綜合、仿真。此程序通過下載到FPGA 芯片后，可應(yīng)用于實(shí)際的數(shù)字鐘顯示中...
上傳時(shí)間： 2013-11-10
上傳用戶：hz07104032
資源簡(jiǎn)介：one of video tool Skype only in windows mobile5.0 more than running, but my task is to let it run Skype in WINCE only in windows mobile5.0 more than running, but my task is to let it run in WINCE . Leave no stone unturned when I can not ge...
上傳時(shí)間： 2014-01-17
上傳用戶：miaochun888
資源簡(jiǎn)介：The exacting technological demands created byincreasing bandwidth requirements have given riseto significant advances in FPGA technology thatenable engineers to successfully incorporate highspeedI/O interfaces in their designs. One aspect o...
上傳時(shí)間： 2013-10-22
上傳用戶：1234xhb
資源簡(jiǎn)介：As businesses and consumers expect more fromportable electronics, the FPGA industry has beencompelled to re-think how it serves these low-power,cost-sensitive markets. Application classes like
上傳時(shí)間： 2013-11-08
上傳用戶：immanuel2006
資源簡(jiǎn)介：aPLib is a 32-bit compression library based on the compression algorithm used in aPACK (my executable packer). aPLib is an easy-to-use alternative to many of the heavy-weight compression libraries available.
上傳時(shí)間： 2013-11-30
上傳用戶：一諾88
資源簡(jiǎn)介：FreeJaPoll is a free software that make possible to add in a simple way a web-survey to your own site. FreeJaPoll is a servlet written in Java programming language the program logo (on the right) shows The Duke (Java mascotte) and a duk...
上傳時(shí)間： 2015-05-16
上傳用戶：無聊來刷下
資源簡(jiǎn)介：Welcome to the Wrox Press C++ tutorial "I hope you ll enjoy reading this tutorial with your portable, your work, or your home PC. It s a perfect companion to the Introduction to Visual C++ 6.0 Standard Edition manual and is a proven aid to...
上傳時(shí)間： 2016-01-26
上傳用戶：wsf950131
資源簡(jiǎn)介：The first task at hand is to set up the endpoints appropriately for this example. The following code switches the CPU clock speed to 48 MHz (since at power-on default it is 12 MHz), and sets up EP2 as a Bulk OUT endpoint, 4x buffered of si...
上傳時(shí)間： 2013-12-02
上傳用戶：dianxin61
資源簡(jiǎn)介：DDR SDRAM控制器的VHDL源代碼，含詳細(xì)設(shè)計(jì)文檔。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The digital Clock M...
上傳時(shí)間： 2014-11-01
上傳用戶：l254587896
資源簡(jiǎn)介：《FPGA數(shù)字電子系統(tǒng)設(shè)計(jì)與開發(fā)實(shí)例導(dǎo)航》的配套光盤，Verilog編寫，USB、I2C、MAC的接口設(shè)計(jì)-"FPGA digital electronic system design and development examples navigation" matching discs, Verilog prepared, USB, I2C, the MAC interface design
上傳時(shí)間： 2017-02-10
上傳用戶：himbly
