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• Traffic light written with Verilog免費(fèi)下載

  資源簡(jiǎn)介：Traffic light written with Verilog

  標(biāo)簽： Traffic Verilog written light

  上傳時(shí)間： 2013-12-10

  上傳用戶：稀世之寶039

• it is a Verilog code written for Traffic light controller will synthesize in xinlix ise 8.2i.i have免費(fèi)下載

  資源簡(jiǎn)介：it is a Verilog code written for Traffic light controller will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].it is a state machine based code.

  標(biāo)簽： controller synthesize Verilog Traffic

  上傳時(shí)間： 2017-03-22

  上傳用戶：xymbian

• Cellular Automata Simulator for one Lane flow with Traffic light免費(fèi)下載

  資源簡(jiǎn)介：Cellular Automata Simulator for one Lane flow with Traffic light

  標(biāo)簽： Simulator Cellular Automata Traffic

  上傳時(shí)間： 2014-01-16

  上傳用戶：葉山豪

• Traffic light CONTROLLER using C51 and RTX-51 tiny免費(fèi)下載

  資源簡(jiǎn)介：Traffic light CONTROLLER using C51 and RTX-51 tiny，This program is a simple Traffic light Controller. Between　start time and end time the system controls a Traffic light with pedestrian self-service. Outside of this time range the yellow ...

  標(biāo)簽： CONTROLLER Traffic light using

  上傳時(shí)間： 2013-12-27

  上傳用戶：123456wh

• This program is a simple Traffic light Controller. Between start time and end time the system contro免費(fèi)下載

  資源簡(jiǎn)介：This program is a simple Traffic light Controller. Between start time and end time the system controls a Traffic light with pedestrian self-service. Outside of this time range the yellow caution lamp is blinking.

  標(biāo)簽： time Controller Between program

  上傳時(shí)間： 2016-01-23

  上傳用戶：iswlkje

• This is a simple MIPS processor datapath written in Verilog hardware language. You can see the signa免費(fèi)下載

  資源簡(jiǎn)介：This is a simple MIPS processor datapath written in Verilog hardware language. You can see the signals when emulating in signalscan. Compile it with Verilog in linux.

  標(biāo)簽： processor datapath hardware language

  上傳時(shí)間： 2017-04-22

  上傳用戶：磊子226

• The Traffic light is timed and lets cars pass during a specific time period. There is a pedestrial免費(fèi)下載

  資源簡(jiǎn)介：The Traffic light is timed and lets cars pass during a specific time period. There is a pedestrial crossing button that lets pedestrians cross. The lights are connected to Port 1. You can see this in action using dScope.

  標(biāo)簽： pedestrial specific Traffic during

  上傳時(shí)間： 2014-01-22

  上傳用戶：cuibaigao

• Traffic light c program for hoteck .免費(fèi)下載

  資源簡(jiǎn)介：Traffic light c program for hoteck .

  標(biāo)簽： Traffic program hoteck light

  上傳時(shí)間： 2015-05-01

  上傳用戶：jcljkh

• mining source code written in Verilog免費(fèi)下載

  資源簡(jiǎn)介：mining source code written in Verilog

  標(biāo)簽： Verilog written mining source

  上傳時(shí)間： 2015-05-06

  上傳用戶：asddsd

• The program was written with some object-orientation in mind, which means that all functions that op免費(fèi)下載

  資源簡(jiǎn)介：The program was written with some object-orientation in mind, which means that all functions that operate on a certain structure, has the structure s name as prefix in the function name, for example "Bitstream_get" which gets bits from a bi...

  標(biāo)簽： object-orientation that functions program

  上傳時(shí)間： 2014-01-15

  上傳用戶：epson850

• VHDL Traffic light control免費(fèi)下載

  資源簡(jiǎn)介：VHDL Traffic light control

  標(biāo)簽： Traffic control light VHDL

  上傳時(shí)間： 2015-07-18

  上傳用戶：gengxiaochao

• a program about Traffic light demo.免費(fèi)下載

  資源簡(jiǎn)介：a program about Traffic light demo.

  標(biāo)簽： program Traffic about light

  上傳時(shí)間： 2014-01-05

  上傳用戶：66666

• DAC converter design with Verilog code and testbench免費(fèi)下載

  資源簡(jiǎn)介：DAC converter design with Verilog code and testbench

  標(biāo)簽： converter testbench Verilog design

  上傳時(shí)間： 2014-01-23

  上傳用戶：yyyyyyyyyy

• The program is written with Vc language,working for logon the net by dialing ,the is a release versi免費(fèi)下載

  資源簡(jiǎn)介：The program is written with Vc language,working for logon the net by dialing ,the is a release version.

  標(biāo)簽： the language program dialing

  上傳時(shí)間： 2016-04-13

  上傳用戶：jichenxi0730

• queue hardware deisgn with Verilog免費(fèi)下載

  資源簡(jiǎn)介：queue hardware deisgn with Verilog

  標(biāo)簽： hardware Verilog deisgn queue

  上傳時(shí)間： 2016-04-23

  上傳用戶：gxrui1991

• the programme is written with java,not my composition by download from the net.免費(fèi)下載

  資源簡(jiǎn)介：the programme is written with java,not my composition by download from the net.

  標(biāo)簽： composition the programme download

  上傳時(shí)間： 2014-03-02

  上傳用戶：hj_18

• FUNDAMENTALS OF DIGITAL LOGIC WITH Verilog DESIGN 將Verilog和數(shù)電很好的結(jié)合在一起講解免費(fèi)下載

  資源簡(jiǎn)介：FUNDAMENTALS OF DIGITAL LOGIC WITH Verilog DESIGN 將Verilog和數(shù)電很好的結(jié)合在一起講解

  標(biāo)簽： FUNDAMENTALS DIGITAL Verilog Verilog

  上傳時(shí)間： 2016-08-20

  上傳用戶：王慶才

• This is an extension of sign example. You can design your own Traffic sign by using Verilog. And the免費(fèi)下載

  資源簡(jiǎn)介：This is an extension of sign example. You can design your own Traffic sign by using Verilog. And the result from Verilog can be seen by the attached C file.

  標(biāo)簽： sign extension Verilog example

  上傳時(shí)間： 2016-10-12

  上傳用戶：haohaoxuexi

• selects the mux channel and configures the MAX197 for second write pulse, written with ACQMOD = 0,免費(fèi)下載

  資源簡(jiǎn)介：selects the mux channel and configures the MAX197 for second write pulse, written with ACQMOD = 0, termi- either unipolar or bipolar input range. A write pulse (WR nates acquisition and starts conversion on WR°Os risin + CS) can either...

  標(biāo)簽： configures the selects channel

  上傳時(shí)間： 2013-12-09

  上傳用戶：

• selects the mux channel and configures the MAX197 for second write pulse, written with ACQMOD = 0,免費(fèi)下載

  資源簡(jiǎn)介：selects the mux channel and configures the MAX197 for second write pulse, written with ACQMOD = 0, termi- either unipolar or bipolar input range. A write pulse (WR nates acquisition and starts conversion on WR°Os risin + CS) can either...

  標(biāo)簽： configures the selects channel

  上傳時(shí)間： 2016-12-24

  上傳用戶：朗朗乾坤

• selects the mux channel and configures the MAX197 for second write pulse, written with ACQMOD = 0,免費(fèi)下載

  資源簡(jiǎn)介：selects the mux channel and configures the MAX197 for second write pulse, written with ACQMOD = 0, termi- either unipolar or bipolar input range. A write pulse (WR nates acquisition and starts conversion on WR°Os risin is restarted. T...

  標(biāo)簽： configures the selects channel

  上傳時(shí)間： 2016-12-24

  上傳用戶：yzhl1988

• Unix Unleashed, Third Edition is written with the power user and system administrator in mind. This免費(fèi)下載

  資源簡(jiǎn)介：Unix Unleashed, Third Edition is written with the power user and system administrator in mind. This book will help the reader understand the nuances of the major Unix variants including SVR4, HP-UX, Solaris, AIX, BSD, IRIX, SunOS, and Linux...

  標(biāo)簽： administrator Unleashed Edition written

  上傳時(shí)間： 2017-01-13

  上傳用戶：來(lái)茴

• example Traffic light by VHDL免費(fèi)下載

  資源簡(jiǎn)介：example Traffic light by VHDL

  標(biāo)簽： example Traffic light VHDL

  上傳時(shí)間： 2017-04-17

  上傳用戶：清風(fēng)冷雨

• light chaser with asm and hex files so that u can directly piut in 89c51免費(fèi)下載

  資源簡(jiǎn)介：light chaser with asm and hex files so that u can directly piut in 89c51

  標(biāo)簽： directly chaser light 89c51

  上傳時(shí)間： 2017-04-18

  上傳用戶：bakdesec

• Booth multiplier written in Verilog免費(fèi)下載

  資源簡(jiǎn)介：Booth multiplier written in Verilog

  標(biāo)簽： multiplier written Verilog Booth

  上傳時(shí)間： 2017-04-22

  上傳用戶：天涯

• it is a 4-bit lcd driver written in Verilog .it will work on spartan 3 xilini devices.免費(fèi)下載

  資源簡(jiǎn)介：it is a 4-bit lcd driver written in Verilog .it will work on spartan 3 xilini devices.

  標(biāo)簽： devices written Verilog spartan

  上傳時(shí)間： 2013-12-07

  上傳用戶：hongmo

• it is a analog i/o interface written in Verilog .it will work on spartan 3 xilini devices.免費(fèi)下載

  資源簡(jiǎn)介：it is a analog i/o interface written in Verilog .it will work on spartan 3 xilini devices.

  標(biāo)簽： interface devices written Verilog

  上傳時(shí)間： 2017-05-24

  上傳用戶：cxl274287265

• these files are written in Verilog but i am uploading in text format免費(fèi)下載

  資源簡(jiǎn)介：these files are written in Verilog but i am uploading in text format

  標(biāo)簽： uploading written Verilog format

  上傳時(shí)間： 2017-06-01

  上傳用戶：520

• these files are written in Verilog but i am uploading in text format免費(fèi)下載

  資源簡(jiǎn)介：these files are written in Verilog but i am uploading in text format

  標(biāo)簽： uploading written Verilog format

  上傳時(shí)間： 2013-12-21

  上傳用戶：wfeel

• these files are written in Verilog but i am uploading in text format免費(fèi)下載

  資源簡(jiǎn)介：these files are written in Verilog but i am uploading in text format

  標(biāo)簽： uploading written Verilog format

  上傳時(shí)間： 2017-06-01

  上傳用戶：wys0120