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  • MAXX9257 MAX9258芯片可編程SerDes持續(xù)時間計算

    The MAX9257/MAX9258 programmable serializer/deserializer (SerDes) devices transfer both video data and control signals over the same twisted-pair cable. However, control data can only be transmitted during the vertical blank time, which is indicated by the control-channel-enabled output (CCEN) signal. The electronic control unit (ECU) firmware designer needs to know how quickly to respond to the CCEN signal before it times out and how to calculate this duration. This application note describes how to calculate the duration of the CCEN for the MAX9257/MAX9258 SerDes chipset. The calculation is based on STO timeout, clock frequency, and UART bit timing. The CCEN duration is programmable and can be closed if not in use.

    標簽: SerDes MAXX 9257 9258

    上傳時間: 2014-01-24

    上傳用戶:xingisme

  • MAX7456在可視倒車雷達中的應(yīng)用

    為解決傳統(tǒng)可視倒車雷達視頻字符疊加器結(jié)構(gòu)復(fù)雜,可靠性差,成本高昂等問題,在可視倒車雷達設(shè)計中采用視頻字符發(fā)生器芯片MAX7456。該芯片集成了所有用于產(chǎn)生用戶定義OSD,并將其插入視頻信號中所需的全部功能,僅需少量的外圍阻容元件即可正常工作。給出了以MAX7456為核心的可視倒車雷達的軟、硬件實現(xiàn)方案及設(shè)計實例。該方案具有電路結(jié)構(gòu)簡單、價格低廉、符合人體視覺習(xí)慣的特點。經(jīng)實際裝車測試,按該方案設(shè)計的可視倒車雷達視場清晰、提示字符醒目、工作可靠,可有效降低駕駛員倒車時的工作強度、減少倒車事故的發(fā)生。 Abstract:  A new video and text generation chip,MAX7456,was used in the design of video parking sensor in order to simplify system structure,improve reliability and reduce cost. This chip included all the necessary functions to generate user-defined OSDs and to add them into the video signals. It could be put into work with addition of just a small number of resistances and capacitors. This paper provided software and hardware implementation solutions and design example based on the chip. The system had the characteristics of simplicity in circuit structure,lower cost,and comfort for the nature of human vision. Loading road test demonstrates high video and text display quality and reliable performance,which makes the driver easy to see backward and reduces chance of accidents.

    標簽: 7456 MAX 可視倒車 中的應(yīng)用

    上傳時間: 2013-12-10

    上傳用戶:qiaoyue

  • 基于ADSP-BF561 的數(shù)字攝像系統(tǒng)設(shè)計

    基于ADSP-BF561的數(shù)字攝像系統(tǒng)設(shè)計Design of Digital video Camera System Based on Digital Signal ProcessorADSP-BF561(浙江大學(xué) 信息與通信工程研究所,浙江 杭州 310027) 馬海杰, 劉云海摘要:介紹了基于ADI雙核的數(shù)字信號處理芯片ADSP-BF561 的數(shù)字攝像系統(tǒng)實現(xiàn)方案。系統(tǒng)包括硬件和軟件兩部分,硬件主要有ADSP-BF561及其外圍電路、音視頻模數(shù)/數(shù)模轉(zhuǎn)換、CF卡/微硬盤接口等部分。軟件主要有操作系統(tǒng)及音視頻編解碼算法等部分。關(guān)鍵詞:ADSP-BF561 ;數(shù)字攝像機;微硬盤;MPEG-4;A/D;D/A中圖分類號:TN948.41文獻標識碼:AAbstract: An implementation of digital video camera system based on ADI dual core digital signal processor ADSP-BF561 is introduced. The system can be divided into two parts——hardware and software design. The hardware design includes ADSP-BF561 and perpheral apparatus, A/D,D/A, CF card or Microdrive and so on. The software includes operating system , audio and video coding algorithm.Key words: ADSP-BF561; digital video camera; microdrive; MPEG-4;A/D;D/A

    標簽: ADSP-BF 561 數(shù)字攝像 系統(tǒng)設(shè)計

    上傳時間: 2013-11-10

    上傳用戶:yl1140vista

  • 基于DSP與FPGA的多視頻通道的切換控制

    為了擴大監(jiān)控范圍,提高資源利用率,降低系統(tǒng)成本,提出了一種多通道視頻切換的解決方案。首先從視頻信號分離出行場信號,然后根據(jù)行場信號由DSP和FPGA產(chǎn)生控制信號,控制多路視頻通道之間的切換,從而實現(xiàn)讓一個視頻處理器同時監(jiān)控不同場景。實驗結(jié)果表明,該方案可以在視頻監(jiān)控告警系統(tǒng)中穩(wěn)定、可靠地實現(xiàn)視頻通道的切換。 Abstract:  To expand the scope of monitoring, improve resource utilization, reduce system cost, a multiple video channels signal switching method is pointed out in this paper. First, horizontal sync signal and field sync signal from the video signal are separated, then control signal according to the sync signal by DSP and FPGA is generated to control the switching between multiple video channels. Thus, it achieves to make a video processor to monitor different place. Experimental results show that the method can realize video channel switching reliably, and is applied in the video monitoring warning system successfully.

    標簽: FPGA DSP 視頻通道 切換控制

    上傳時間: 2013-11-09

    上傳用戶:不懂夜的黑

  • WP328-FPGA的語音數(shù)據(jù)融合

      The SDI standards are the predominant standards for uncompressed digital videointerfaces in the broadcast studio and video production center. The first SDI standard,SD-SDI, allowed standard-definition digital video to be transported over the coaxial cableinfrastructure initially installed in studios to carry analog video. Next, HD-SDI wasto support high-definition video. Finally, dual link HD-SDI and 3G-SDIdoubled the bandwidth of HD-SDI to support 1080p (50 Hz and 60 Hz) and other videoformats requiring more bandwidth than HD-SDI provides.

    標簽: FPGA 328 WP 語音

    上傳時間: 2013-10-08

    上傳用戶:yjj631

  • XAPP740利用AXI互聯(lián)設(shè)計高性能視頻系統(tǒng)

    This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX  and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board

    標簽: XAPP 740 AXI 互聯(lián)

    上傳時間: 2013-11-14

    上傳用戶:fdmpy

  • 基于Actel FPGA的VGA顯示控制方案

    VGA 是視頻圖形陣列(video Graphics Array)的簡稱,是IBM 于1987 年提出的一個使用模擬信號的圖形顯示標準。最初的VGA 標準最大只能支持640*480 分辨率的顯示器,而為了適應(yīng)大屏幕的應(yīng)用,視頻電氣標準化組織VESA(video Electronics StandardsAssociation 的簡稱)將VGA 標準擴展為SVGA 標準,SVGA 標準能夠支持更大的分辨率。人們通常所說的VGA 實際上指的就是VESA 制定的SVGA 標準。(1). VGA 接口VGA 采用15 針的接口,用于顯示的接口信號主要有5 個:1 個行同步信號、1 個場同步信號以及3 個顏色信號,接口還包含自測試以及地址碼信號,一般由不同的制造商定義,主要用來進行測試及支持其它功能。

    標簽: Actel FPGA VGA 顯示控制

    上傳時間: 2013-10-27

    上傳用戶:541657925

  • H.264碼流結(jié)構(gòu)解析

    MPEG(Moving Picture Experts Group)和VCEG(video Coding Experts Group)已經(jīng)聯(lián)合開發(fā)了一個比早期研發(fā)的MPEG 和H.263 性能更好的視頻壓縮編碼標準,這就是被命名為AVC(Advanced video Coding),也被稱為ITU-T H.264 建議和MPEG-4 的第10 部分的標準,簡稱為H.264/AVC 或H.264。這個國際標準已經(jīng)與2003 年3 月正式被ITU-T 所通過并在國際上正式頒布。為適應(yīng)高清視頻壓縮的需求,2004 年又增加了FRExt 部分;為適應(yīng)不同碼率及質(zhì)量的需求,2006 年又增加了可伸縮編碼 SVC。

    標簽: 264 碼流

    上傳時間: 2013-11-19

    上傳用戶:dancnc

  • S參數(shù)的設(shè)計與應(yīng)用

    Agilent AN 154 S-Parameter Design Application Note S參數(shù)的設(shè)計與應(yīng)用 The need for new high-frequency, solid-state circuitdesign techniques has been recognized both by microwaveengineers and circuit designers. These engineersare being asked to design solid state circuitsthat will operate at higher and higher frequencies.The development of microwave transistors andAgilent Technologies’ network analysis instrumentationsystems that permit complete network characterizationin the microwave frequency rangehave greatly assisted these engineers in their work.The Agilent Microwave Division’s lab staff hasdeveloped a high frequency circuit design seminarto assist their counterparts in R&D labs throughoutthe world. This seminar has been presentedin a number of locations in the United States andEurope.From the experience gained in presenting this originalseminar, we have developed a four-part videotape, S-Parameter Design Seminar. While the technologyof high frequency circuit design is everchanging, the concepts upon which this technologyhas been built are relatively invariant.The content of the S-Parameter Design Seminar isas follows:

    標簽: S參數(shù)

    上傳時間: 2013-12-19

    上傳用戶:aa54

  • 基于ARM的遠程無線視頻監(jiān)控終端設(shè)計

    提出了一種以ARM微處理器為控制核心的遠程無線視頻監(jiān)控終端的設(shè)計方案,其監(jiān)控終端的硬件設(shè)計包括視頻采集處理、中央管理控制、無線傳輸3個模塊。并給出了監(jiān)控終端的軟件開發(fā)平臺和開發(fā)模式的系統(tǒng)啟動代碼、嵌入式Linux系統(tǒng)移植以及驅(qū)動程序和應(yīng)用程序。測試結(jié)果表明,該監(jiān)控終端設(shè)計方案合理、有效,基本滿足監(jiān)控需求。 Abstract:  A remote wireless video monitoring terminal design, which uses ARM microprocessor as its core control, is proposed in this paper.The hardware design of monitoring terminal system is composed of the video acquisition and processing module, the central management and control module, wireless transmission module.Meanwhile the monitoring terminal-s software development platform and development patterns are designed. Also the design of the system-s start codes, embedded Linux system-s transplantation process, driver and the corresponding applications are given. The results showed that the monitoring terminal design is reasonable, effective, basically meet monitoring requirements.

    標簽: ARM 遠程無線 視頻監(jiān)控 終端設(shè)計

    上傳時間: 2013-11-13

    上傳用戶:wanqunsheng

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