此曼徹斯特碼的解碼程序是采用VHDL硬件語言編寫的。
上傳時(shí)間： 2013-09-06
上傳用戶：zhouli
用vhdl編寫的基于fpga的數(shù)字頻率計(jì)程序算法
標(biāo)簽： vhdl fpga 編寫 數(shù)字頻率計(jì)
上傳時(shí)間： 2013-09-07
上傳用戶：chfanjiang
LPC2106的雙機(jī)SPI通訊,帶PROTEUS仿真.收發(fā)程序均有.
上傳時(shí)間： 2013-09-30
上傳用戶：tyler
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
標(biāo)簽： Modelling Guide Navy VHDL
上傳時(shí)間： 2014-12-23
上傳用戶：xinhaoshan2016
本文詳細(xì)討論了VHDL語句對(duì)PLD設(shè)計(jì)的影響和設(shè)計(jì)經(jīng)驗(yàn)，經(jīng)典文章，值得仔細(xì)閱讀消化。,PLD Programming Using VHDL
標(biāo)簽： Programming Using VHDL PLD
上傳時(shí)間： 2013-11-17
上傳用戶：teddysha
本文簡(jiǎn)單討論并總結(jié)了VHDL、Verilog，System verilog 這三中語言的各自特點(diǎn)和區(qū)別As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.
標(biāo)簽： Verilog verilog System VHDL
上傳時(shí)間： 2013-10-16
上傳用戶：牛布牛
多功能數(shù)字鐘的VHDL設(shè)計(jì)
上傳時(shí)間： 2013-10-29
上傳用戶：swz13842860183
51單片機(jī)綜合學(xué)習(xí)系統(tǒng)-SPI總線
標(biāo)簽： SPI 51單片機(jī) 學(xué)習(xí)系統(tǒng) 總線
上傳時(shí)間： 2014-01-27
上傳用戶：fudong911
SPI總線在51單片機(jī)系統(tǒng)中的實(shí)現(xiàn)
標(biāo)簽： SPI 51單片機(jī) 總線 中的實(shí)現(xiàn)
上傳時(shí)間： 2013-11-15
上傳用戶：haoxiyizhong
基于MSP430的模擬SPI串口通信的實(shí)現(xiàn)
上傳時(shí)間： 2013-11-23
上傳用戶：wfymay
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