Use verilog and VHDL to implement the Motion Estimation function, work as the hardware accelerator.
標簽： accelerator Estimation implement the
上傳時間： 2016-05-25
上傳用戶：jing911003
This file contains a selection of VHDL source files which serve to illustrate the diversity and power of the language when used to describe various types of hardware. The examp terms of basic logic gates, to more complex systems, such as a behavioural model of a microprocessor and associated memory. All of the examples can be simulated using any synthesised using current synthesis tools.
標簽： illustrate diversity selection contains
上傳時間： 2016-06-06
上傳用戶：yimoney
JLAB is a set of Matlab functions I have written or co-written over the past fifteen years for the purpose of analyzing data. It consists of four hundred m-files spanning thirty thousand lines of code. JLAB includes functions ranging in complexity from one-line aliases to high-level algorithms for certain specialized tasks. These have been collected together and made publicly available for you to use, modify, and --- subject to certain very reasonable constraints --- to redistribute. Some of the highlights are: a suite of functions for the rapid manipulation of multi-component, potentially multi-dimensional datasets a systematic way of dealing with datasets having components of non-uniform length tools for fine-tuning figures using compact, straightforward statements and specialized functions for spectral and time / frequency analysis, including advanced wavelet algorithms developed by myself and collaborators.
標簽： co-written functions the fifteen
上傳時間： 2014-01-26
上傳用戶：hjshhyy
vhdl程序 Uncomment the following lines to use the declarations that are provided for instantiating Xilinx primitive components.
標簽： instantiating declarations Uncomment the
上傳時間： 2013-12-21
上傳用戶：CHENKAI
The Free IP Project VHDL Free-RAM Core
標簽： Free-RAM Project Free Core
上傳時間： 2016-12-19
上傳用戶：xinzhch
VHDL, the transfer of data types
上傳時間： 2013-12-16
上傳用戶：iswlkje
1. Learn the basic constructs of VHDL 2. Learn the modeling structure of VHDL 3. Understand the design environments – Simulation – Synthesis
標簽： the Learn VHDL Understand
上傳時間： 2017-02-18
上傳用戶：love_stanford
The Synthetic PIC Verion 1.1 This a VHDL synthesizable model of a simple PIC 16C5x microcontroller. It is not, and is not intended as, a high fidelity circuit simulation. This package includes the following files. Note that the license agreement is stated in the main VHDL file, PICCPU.VHD and common questions are answered in the file SYNTHPIC.TXT Files: README.TXT This file.. SYNTHPIC.TXT Questions and Answers PICCPU.VHD Main processor VHDL file PICALU.VHD ALU for the PICCPU PICREGS.VHD Data memory PICROM.VHD Program memory (created by HEX2VHDL utility) PICTEST.VHD Simple test bench I used to do testing (optional) PICTEST.CMD My Viewlogic ViewSim command file (again, optional) TEST1.ASM First program I assembled and ran on it. TEST2.ASM Another test program.. TEST3.ASM Yet another.. TEST4.ASM Yet another.. TEST5.ASM Yet another.. TEST6.ASM Yet another.. HEX2VHDL.CPP Utility for converting
標簽： synthesizable microcontro Synthetic PIC
上傳時間： 2013-12-22
上傳用戶：妄想演繹師
this is a implementation of the 16 bit loop back in vhdl
標簽： implementation this back loop
上傳時間： 2013-12-04
上傳用戶：asdfasdfd
vhdl show the char on vga monitor
上傳時間： 2017-03-09
上傳用戶：yyyyyyyyyy
