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the-VHDL-co

  • ZBT SRAM控制器參考設(shè)計(jì),xilinx提供VHDL代碼

    ZBT SRAM控制器參考設(shè)計(jì),xilinx提供VHDL代碼 Description:   Contains the following files     readme.txt appnote_zbtp.vhd appnote_zbtf.vhd appnote_zbt.ucf Platform:   All Installation/Use:   Use 'unzip' on the .zip file and 'gunzip' followed by 'tar -xvf' on the .tar.gz file.

    標(biāo)簽: xilinx SRAM VHDL ZBT

    上傳時(shí)間: 2013-10-25

    上傳用戶:peterli123456

  • USB接口控制器參考設(shè)計(jì),xilinx提供VHDL代碼 us

    USB接口控制器參考設(shè)計(jì),xilinx提供VHDL代碼 usb xilinx vhdl ;  This program is free software; you can redistribute it and/or modify ;  it under the terms of the GNU General Public License as published by ;  the Free Software Foundation; either version 2 of the License, or ;  (at your option) any later version. ;      ;  This program is distributed in the hope that it will be useful, ;  but WITHOUT ANY WARRANTY; without even the implied warranty of ;  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the ;  GNU General Public License for more details. ;      ;  You should have received a copy of the GNU General Public License ;  along with this program; if not, write to the Free Software ;  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

    標(biāo)簽: xilinx VHDL USB us

    上傳時(shí)間: 2013-10-29

    上傳用戶:zhouchang199

  • ref sdr sdram vhdl代碼

    ref-sdr-sdram-vhdl代碼 SDR SDRAM Controller v1.1 readme.txt This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1. The PLL is targeted at APEX(TM) devices. Please regenerate for your chosen architecture. Last updated September, 2002 Copyright ?2002 Altera Corporation. All rights reserved.

    標(biāo)簽: sdram vhdl ref sdr

    上傳時(shí)間: 2013-10-23

    上傳用戶:半熟1994

  • UART 4 UART參考設(shè)計(jì),Xilinx提供VHDL代碼

    UART 4 UART參考設(shè)計(jì),Xilinx提供VHDL代碼 uart_vhdl This zip file contains the following folders:  \vhdl_source  -- Source VHDL files:      uart.vhd  - top level file      txmit.vhd - transmit portion of uart      rcvr.vhd -  - receive portion of uart \vhdl_testfixture  -- VHDL Testbench files. This files only include the testbench behavior, they         do not instantiate the DUT. This can easily be done in a top-level VHDL          file or a schematic. This folder contains the following files:      txmit_tb.vhd  -- Test bench for txmit.vhd.      rcvr_tf.vhd  -- Test bench for rcvr.vhd.

    標(biāo)簽: UART Xilinx VHDL 參考設(shè)計(jì)

    上傳時(shí)間: 2013-11-02

    上傳用戶:18862121743

  • A high quality VC++ source code implementing the very important context-based adaptive arithmetic co

    A high quality VC++ source code implementing the very important context-based adaptive arithmetic coder.

    標(biāo)簽: context-based implementing arithmetic important

    上傳時(shí)間: 2015-04-10

    上傳用戶:changeboy

  • CC386 is a general-purpose 32-bit C compiler. It is not an optimizing compiler but given that the co

    CC386 is a general-purpose 32-bit C compiler. It is not an optimizing compiler but given that the code generation is fairly good. There are two versions one is for MSDOS/DPMI and one is for Win32. The Win32 version has a full-blown IDE capable of editing, building, and debugging windows programs included with it. However at this time debugging support for MSDOS is rudimentary at best and there is no IDE for DOS. the newest version, support windows.

    標(biāo)簽: compiler general-purpose optimizing given

    上傳時(shí)間: 2015-04-12

    上傳用戶:gtzj

  • -- Title : Barrel Shifter (Pure combinational) -- This VHDL design file is an open design you can r

    -- Title : Barrel Shifter (Pure combinational) -- This VHDL design file is an open design you can redistribute it and/or -- modify it and/or implement it after contacting the author -- You can check the draft license at

    標(biāo)簽: design combinational Shifter Barrel

    上傳時(shí)間: 2014-12-21

    上傳用戶:784533221

  • VHDL源代碼.設(shè)計(jì)一個(gè)帶有異步清0功能的十進(jìn)制計(jì)數(shù)器。計(jì)數(shù)器時(shí)鐘clk上升沿有效

    VHDL源代碼.設(shè)計(jì)一個(gè)帶有異步清0功能的十進(jìn)制計(jì)數(shù)器。計(jì)數(shù)器時(shí)鐘clk上升沿有效,清零端為clrn,進(jìn)位輸出為co。

    標(biāo)簽: VHDL clk 源代碼 十進(jìn)制計(jì)數(shù)器

    上傳時(shí)間: 2014-11-21

    上傳用戶:xc216

  • This code was used for making the practical measurements in section 2.3 of my thesis. This Matlab co

    This code was used for making the practical measurements in section 2.3 of my thesis. This Matlab code allows an OFDM signal to be generated based on an input data file. The data can be random data, a grey scale image, a wave file, or any type of file. The generated OFDM signal is stored as a windows wave file, allowing it to be viewed, listened to and manipulated in other programs. The modified wave file can then be decoded by the receiver software to extract the original data. This code was developed for the experiments that I performed in my honours thesis, and thus has not been fully debugged. This is the original code developed for the thesis and so has several problems with it. The BER performance given by the simulations is infact Symbol Error Rate.

    標(biāo)簽: This measurements practical section

    上傳時(shí)間: 2015-09-20

    上傳用戶:tedo811

  • Calculates photonic band structure for either the bcc lattice of dielectric spheres of dielectric co

    Calculates photonic band structure for either the bcc lattice of dielectric spheres of dielectric constant epsilon_a in a dielectric background of dielectric constant epsilon_b.

    標(biāo)簽: dielectric Calculates structure photonic

    上傳時(shí)間: 2015-10-08

    上傳用戶:skhlm

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