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opengl-guide

  • 無線技術指南

    Radio frequency (RF) can be a complex subject to navigate, but it does not have to be. If you are just getting started with radios or maybe you cannot find that old reference book about antenna aperture, this guide can help. It is intended to provide a basic understanding of RF technology, as well act as a quick reference for those who “know their stuff” but may be looking to brush up on that one niche term that they never quite understood. This document is also a useful reference for Maxim’s products and data sheets, an index to deeper analysis found in our application notes, and a general reference for all things RF.

    標簽: 無線技術

    上傳時間: 2013-10-08

    上傳用戶:kinochen

  • 如何用C來完成SN8系列芯片的程序設計

    松翰 C語言 編程 指導C +Program +Guide

    標簽: SN8 系列芯片 程序設計

    上傳時間: 2013-10-31

    上傳用戶:zhaistone

  • The Design Warrior Guide To FPGA

    FPGA推薦好書免費下載

    標簽: Warrior Design Guide FPGA

    上傳時間: 2013-11-06

    上傳用戶:hebanlian

  • AXI參考指南(英文資料)

    AXI Reference Guide (AXI).pdf

    標簽: AXI 英文

    上傳時間: 2013-10-29

    上傳用戶:libinxny

  • Nios II 系列處理器配置選項

        Nios II 系列處理器配置選項:This chapter describes the Nios® II Processor parameter editor in Qsys and SOPC Builder. The Nios II Processor parameter editor allows you to specify the processor features for a particular Nios II hardware system. This chapter covers the features of the Nios II processor that you can configure with the Nios II Processor parameter editor; it is not a user guide for creating complete Nios II processor systems.

    標簽: Nios II 列處理器

    上傳時間: 2015-01-01

    上傳用戶:mahone

  • XAPP452-Spartan-3高級配置架構

    This application note provides a detailed description of the Spartan™-3 configurationarchitecture. It explains the composition of the bitstream file and how this bitstream isinterpreted by the configuration logic to program the part. Additionally, a methodology ispresented that will guide the user through the readback process. This information can be usedfor partial reconfiguration or partial readback.

    標簽: Spartan XAPP 452 架構

    上傳時間: 2013-11-16

    上傳用戶:qingdou

  • Virtex-6 FPGA PCB設計手冊

    Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.

    標簽: Virtex FPGA PCB 設計手冊

    上傳時間: 2013-11-11

    上傳用戶:zwei41

  • DS306-PPC405 Virtex-4 Wrapper

    The PPC405 Virtex-4 is a wrapper around the Virtex-4PowerPC™ 405 Processor Block primitive. For detailsregarding the PowerPC 405, see the PowerPC 405 ProcessorBlock Reference Guide.

    標簽: Wrapper Virtex 306 405

    上傳時間: 2015-01-02

    上傳用戶:JIUSHICHEN

  • US Navy VHDL Modelling Guide

      This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.

    標簽: Modelling Guide Navy VHDL

    上傳時間: 2013-11-20

    上傳用戶:pzw421125

  • Guide to HDL Coding Styles for Synthesis

    這篇文章討論了不同HDL代碼的編寫方式,對綜合結果的影響。閱讀本文對深入了解綜合工具和提高HDL的編寫水平有不少幫助,原文時針對Synopsys的綜合軟件論述的,但對所有綜合軟件,都有普遍的借鑒意義  

    標簽: Synthesis Coding Styles Guide

    上傳時間: 2014-01-11

    上傳用戶:亞亞娟娟123

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