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jftp-src-test

  • ADC轉(zhuǎn)換器技術(shù)用語 (A/D Converter Defi

    ANALOG INPUT BANDWIDTH is a measure of the frequencyat which the reconstructed output fundamental drops3 dB below its low frequency value for a full scale input. Thetest is performed with fIN equal to 100 kHz plus integer multiplesof fCLK. The input frequency at which the output is −3dB relative to the low frequency input signal is the full powerbandwidth.APERTURE JITTER is the variation in aperture delay fromsample to sample. Aperture jitter shows up as input noise.APERTURE DELAY See Sampling Delay.BOTTOM OFFSET is the difference between the input voltagethat just causes the output code to transition to the firstcode and the negative reference voltage. Bottom Offset isdefined as EOB = VZT–VRB, where VZT is the first code transitioninput voltage and VRB is the lower reference voltage.Note that this is different from the normal Zero Scale Error.CONVERSION LATENCY See PIPELINE DELAY.CONVERSION TIME is the time required for a completemeasurement by an analog-to-digital converter. Since theConversion Time does not include acquisition time, multiplexerset up time, or other elements of a complete conversioncycle, the conversion time may be less than theThroughput Time.DC COMMON-MODE ERROR is a specification which appliesto ADCs with differential inputs. It is the change in theoutput code that occurs when the analog voltages on the twoinputs are changed by an equal amount. It is usually expressed in LSBs.

    標(biāo)簽: Converter Defi ADC 轉(zhuǎn)換器

    上傳時間: 2013-11-12

    上傳用戶:pans0ul

  • 電腦主板生產(chǎn)工藝及流程

    隨著科學(xué)技術(shù)的不斷發(fā)展,人們的生活水平的不斷提高,通信技術(shù)的不斷擴延,計算機已經(jīng)涉及到各個不同的行業(yè),成為人們生活、工作、學(xué)習(xí)、娛樂不可缺少的工具。而計算機主板作為計算機中非常重要的核心部件,其品質(zhì)的好壞直接影響計算機整體品質(zhì)的高低。因此在生產(chǎn)主板的過程中每一步都是要嚴(yán)格把關(guān)的,不能有絲毫的懈怠,這樣才能使其品質(zhì)得到保證。 基于此,本文主要介紹電腦主板的SMT生產(chǎn)工藝流程和F/T(Function Test)功能測試步驟(F/T測試步驟以惠普H310機種為例)。讓大家了解一下完整的計算機主板是如何制成的,都要經(jīng)過哪些工序以及如何檢測產(chǎn)品質(zhì)量的。 本文首先簡單介紹了PCB板的發(fā)展歷史,分類,功能及發(fā)展趨勢,SMT及SMT產(chǎn)品制造系統(tǒng),然后重點介紹了SMT生產(chǎn)工藝流程和F/T測試步驟。

    標(biāo)簽: 電腦主板 生產(chǎn)工藝 流程

    上傳時間: 2013-11-06

    上傳用戶:paladin

  • pcb layout design(臺灣硬件工程師15年經(jīng)驗

    PCB LAYOUT 術(shù)語解釋(TERMS)1. COMPONENT SIDE(零件面、正面)︰大多數(shù)零件放置之面。2. SOLDER SIDE(焊錫面、反面)。3. SOLDER MASK(止焊膜面)︰通常指Solder Mask Open 之意。4. TOP PAD︰在零件面上所設(shè)計之零件腳PAD,不管是否鑽孔、電鍍。5. BOTTOM PAD:在銲錫面上所設(shè)計之零件腳PAD,不管是否鑽孔、電鍍。6. POSITIVE LAYER:單、雙層板之各層線路;多層板之上、下兩層線路及內(nèi)層走線皆屬之。7. NEGATIVE LAYER:通常指多層板之電源層。8. INNER PAD:多層板之POSITIVE LAYER 內(nèi)層PAD。9. ANTI-PAD:多層板之NEGATIVE LAYER 上所使用之絕緣範(fàn)圍,不與零件腳相接。10. THERMAL PAD:多層板內(nèi)NEGATIVE LAYER 上必須零件腳時所使用之PAD,一般稱為散熱孔或?qū)住?1. PAD (銲墊):除了SMD PAD 外,其他PAD 之TOP PAD、BOTTOM PAD 及INNER PAD 之形狀大小皆應(yīng)相同。12. Moat : 不同信號的 Power& GND plane 之間的分隔線13. Grid : 佈線時的走線格點2. Test Point : ATE 測試點供工廠ICT 測試治具使用ICT 測試點 LAYOUT 注意事項:PCB 的每條TRACE 都要有一個作為測試用之TEST PAD(測試點),其原則如下:1. 一般測試點大小均為30-35mil,元件分布較密時,測試點最小可至30mil.測試點與元件PAD 的距離最小為40mil。2. 測試點與測試點間的間距最小為50-75mil,一般使用75mil。密度高時可使用50mil,3. 測試點必須均勻分佈於PCB 上,避免測試時造成板面受力不均。4. 多層板必須透過貫穿孔(VIA)將測試點留於錫爐著錫面上(Solder Side)。5. 測試點必需放至於Bottom Layer6. 輸出test point report(.asc 檔案powerpcb v3.5)供廠商分析可測率7. 測試點設(shè)置處:Setup􀃆pads􀃆stacks

    標(biāo)簽: layout design pcb 硬件工程師

    上傳時間: 2013-10-22

    上傳用戶:pei5

  • pcb layout規(guī)則

    LAYOUT REPORT .............. 1   目錄.................. 1     1. PCB LAYOUT 術(shù)語解釋(TERMS)......... 2     2. Test Point : ATE 測試點供工廠ICT 測試治具使用............ 2     3. 基準(zhǔn)點 (光學(xué)點) -for SMD:........... 4     4. 標(biāo)記 (LABEL ING)......... 5     5. VIA HOLE PAD................. 5     6. PCB Layer 排列方式...... 5     7.零件佈置注意事項 (PLACEMENT NOTES)............... 5     8. PCB LAYOUT 設(shè)計............ 6     9. Transmission Line ( 傳輸線 )..... 8     10.General Guidelines – 跨Plane.. 8     11. General Guidelines – 繞線....... 9     12. General Guidelines – Damping Resistor. 10     13. General Guidelines - RJ45 to Transformer................. 10     14. Clock Routing Guideline........... 12     15. OSC & CRYSTAL Guideline........... 12     16. CPU

    標(biāo)簽: layout pcb

    上傳時間: 2013-12-20

    上傳用戶:康郎

  • 三種布局的半橋諧振變換器的分析研究

    驅(qū)動電路的設(shè)計是LED照明設(shè)備中的核心部分,驅(qū)動電路的好壞直接影響到了光源是否高效節(jié)能工作。而基于不對稱式半橋諧振變換器設(shè)計的驅(qū)動電路在大功率LED中應(yīng)用較多,本文即針對不對稱式半橋諧振變換器進行了分析,橫向?qū)Ρ萐RC、PRC、LLC諧振變換器后,對性能最好的不對稱式半橋LLC諧振變換器做仿真分析,獲得了相關(guān)計算數(shù)據(jù),驗證了LLC不對稱式半橋諧振器具有優(yōu)良性能,并提出了優(yōu)化方法。

    標(biāo)簽: 布局 半橋諧振 變換器

    上傳時間: 2013-11-18

    上傳用戶:swaylong

  • Lakewood (MAXREFDES7#)3.3V Input, ±12V (±15V) Output Isolated Power Supply

    Abstract: This document details the Lakewood (MAXREFDES7#) subsystem reference design, a 3.3V input, ±12V (±15V) output, isolated power supply. The Lakewood reference design includes a 3W primary-side transformer H-bridge driver for isolated supplies, and two wide input range and adjustable output low-dropout linear regulators (LDOs). Test results and hardware files are included.

    標(biāo)簽: MAXREFDES Lakewood Isolated Output

    上傳時間: 2013-11-02

    上傳用戶:fengzimili

  • Riverside (MAXREFDES8#)3.3V Input, 12V (15V) Output Isolated Power Supply

    Abstract: This document details the Riverside (MAXREFDES8#) subsystem reference design, a 3.3V input, 12V (15V) output, isolated power supply. The Riverside reference design includes a 3W primary-side transformer H-bridge driver for isolated supplies, and one wide input range and adjustable output low-dropout linear regulator (LDO). Test results and hardware files are included.

    標(biāo)簽: Riverside MAXREFDES Isolated Output

    上傳時間: 2013-11-16

    上傳用戶:會稽劍客

  • 隔離電源設(shè)計手冊

    Abstract: This document details the Oceanside (MAXREFDES9#) subsystem reference design, a 3.3V to 15V input,±15V (±12V) output, isolated power supply. The Oceanside design includes a high-efficiency step-up controller, a36V H-bridge transformer driver for isolated supplies, a wide input range, and adjustable output low-dropout linearregulator (LDO). Test results and hardware files are included.  

    標(biāo)簽: 隔離電源 設(shè)計手冊

    上傳時間: 2013-10-12

    上傳用戶:jinyao

  • 如何設(shè)計一個高效率的DC-DC轉(zhuǎn)換器

    Abstract: The DS1875 features a pulse-width modulation (PWM) controller that can be used to control aDC-DC converter. The DC-DC converter can then be used to generate the high bias voltages necessaryfor avalanche photodiodes (APDs). This application note describes the operation of a boost converterthat uses the DS1875. Discussion covers the selection of the inductor and switching frequency, and theselection of components that improve the efficiency of the converter. Test data are presented.

    標(biāo)簽: DC-DC 如何設(shè)計 高效率 轉(zhuǎn)換器

    上傳時間: 2013-10-26

    上傳用戶:lyson

  • 基于IR2101最大功率跟蹤逆變器的設(shè)計

    為解決直流逆變交流的問題,有效地利用能源,讓電源輸出最大功率,設(shè)計了高性能的基于IR2101最大功率跟蹤逆變器,并以SPMC75F2413A單片機作為主控制器。高電壓、高速功率的MOSFET或IGBT驅(qū)動器IR2101采用高度集成的電平轉(zhuǎn)換技術(shù),同時上管采用外部自舉電容上電,能夠穩(wěn)定高效地驅(qū)動MOS管。該逆變器可以實現(xiàn)DC/AC的轉(zhuǎn)換,最大功率點的跟蹤等功能。實際測試結(jié)果表明,該逆變器系統(tǒng)具有跟蹤能力強,穩(wěn)定性高,反應(yīng)靈敏等特點,該逆變器不僅可應(yīng)用于普通的電源逆變系統(tǒng),而且可應(yīng)用于光伏并網(wǎng)發(fā)電的逆變系統(tǒng),具有廣泛的市場前景。 Abstract:  To solve the problem of DC-AC inverter, and to utilize solar energy more efficiently, the design of maximum power point tracking inverter based on IR2101 was achieved with a high-performance, which can make the system output power maximum. SPMC75F2413A was adopted as main controller. IR2101 is a high voltage, high speed power MOSFET and IGBT driver. It adopted highly integrated voltage level transforming technology, and an external bootstrap capacitor was used, which could drive MOS tube efficiently and stably. Many functions are achieved in the system, such as DC/AC conversion, maximun power point tracking, etc. The actual test result shows that the inverter system has characteristics of strong tracking ability, high stability and reacting quickly. The design can not only be used in ordinary power inverter system, but also be used in photovoltaic power inverter system. The design has certain marketing prospects

    標(biāo)簽: 2101 IR 最大功率跟蹤 逆變器

    上傳時間: 2013-11-17

    上傳用戶:lliuhhui

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