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in-memory

  • LPC4300系列ARM雙核微控制器產品數據手冊

    The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated in the core.The LPC4350/30/20/10 include an ARM Cortex-M0 coprocessor, up to 264 kB of datamemory, advanced configurable peripherals such as the State Configurable Timer (SCT)and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals

    標簽: 4300 LPC ARM 雙核微控制器

    上傳時間: 2013-10-28

    上傳用戶:15501536189

  • LPC1300系列產品勘誤數據手冊

    On the LPC13xx, programming, erasure and re-programming of the on-chip flash can be performed using In-System Programming (ISP) via the UART serial port, and also, can be performed using In-Application Programming (IAP) calls directed by the end-user code. For In-System Programming (ISP) via the UART serial port, the ISP command handler (resides in the bootloader) allows erasure of one or more sector (s) of the on-chip flash memory.

    標簽: 1300 LPC 勘誤 數據手冊

    上傳時間: 2013-12-13

    上傳用戶:lmq0059

  • 時鐘恢復設計_英文版

    Today in many applications such as network switches, routers, multi-computers,and processor-memory interfaces, the ability to integrate hundreds of multi-gigabit I/Os is desired to make better use of the rapidly advancing IC technology.

    標簽: 時鐘恢復 英文

    上傳時間: 2013-10-30

    上傳用戶:ysjing

  • MAXQUSBJTAGOW評估板軟件

    MAXQUSBJTAGOW評估板軟件:關鍵特性 Easily Load and Debug Code Interface Provides In-Application Debugging Features Step-by-Step Execution Tracing Breakpointing by Code Address, Data Memory Address, or Register Access Data Memory View and Edit Supports Logic Levels from 1.1V to 3.6V Supports JTAG and 1-Wire Protocols Each Adapter Has Its Own Unique Serial ID, Allowing Multiple Adapters to be Connected Without COM Port Conflicts Has In-Field Upgradable Capability if Firmware Needs to be Upgraded Enclosure Protects from Shorts and ESD

    標簽: MAXQUSBJTAGOW 評估板 軟件

    上傳時間: 2013-10-24

    上傳用戶:teddysha

  • MAXQUSBJTAGOW評估板軟件

    MAXQUSBJTAGOW評估板軟件:關鍵特性 Easily Load and Debug Code Interface Provides In-Application Debugging Features Step-by-Step Execution Tracing Breakpointing by Code Address, Data Memory Address, or Register Access Data Memory View and Edit Supports Logic Levels from 1.1V to 3.6V Supports JTAG and 1-Wire Protocols Each Adapter Has Its Own Unique Serial ID, Allowing Multiple Adapters to be Connected Without COM Port Conflicts Has In-Field Upgradable Capability if Firmware Needs to be Upgraded Enclosure Protects from Shorts and ESD

    標簽: MAXQUSBJTAGOW 評估板 軟件

    上傳時間: 2013-11-23

    上傳用戶:truth12

  • 怎樣使用Nios II處理器來構建多處理器系統

    怎樣使用Nios II處理器來構建多處理器系統 Chapter 1. Creating Multiprocessor Nios II Systems Introduction to Nios II Multiprocessor Systems . . . . . . . . . . . . . . 1–1 Benefits of Hierarchical Multiprocessor Systems  . . . . . . . . . . . . . . . 1–2 Nios II Multiprocessor Systems . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . 1–2 Multiprocessor Tutorial Prerequisites   . . . . . . . . . . .  . . . . . . . . . . . . 1–3 Hardware Designs for Peripheral Sharing   . . . . . . . . . . . .. . . . . . . . 1–3 Autonomous Multiprocessors   . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . 1–3 Multiprocessors that Share Peripherals . . . . . . . . . . . . . . . . . . . . . . 1–4 Sharing Peripherals in a Multiprocessor System   . . . . . . . . . . . . . . . . . 1–4 Sharing Memory  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6 The Hardware Mutex Core  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . 1–7 Sharing Peripherals   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 1–8 Overlapping Address Space  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . 1–8 Software Design Considerations for Multiple Processors . . .. . . . . 1–9 Program Memory  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9 Boot Addresses  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1–13 Debugging Nios II Multiprocessor Designs  . . . . . . . . . . . . . . . .  1–15 Design Example: The Dining Philosophers’ Problem   . . . . .. . . 1–15 Hardware and Software Requirements . . . . . . . . . . . . . . . .. . . 1–16 Installation Notes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–17 Creating the Hardware System   . . . . . . . . . . . . . . .. . . . . . 1–17 Getting Started with the multiprocessor_tutorial_start Design Example   1–17 Viewing a Philosopher System   . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . 1–18 Philosopher System Pipeline Bridges  . . . . . . . . . . . . . . . . . . . . . 1–19 Adding Philosopher Subsystems   . . . . . . . . . . . . . . . . . . . . . .  . . . . 1–21 Connecting the Philosopher Subsystems  . . . . . . . . . . . . .. . . . . 1–22 Viewing the Complete System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–27 Generating and Compiling the System   . . . . . . . . . . . . . . . . . .. 1–28

    標簽: Nios 處理器 多處理器

    上傳時間: 2013-11-21

    上傳用戶:lo25643

  • 使用Nios II緊耦合存儲器教程

                 使用Nios II緊耦合存儲器教程 Chapter 1. Using Tightly Coupled Memory with the Nios II Processor Reasons for Using Tightly Coupled Memory  . . . . . . . . . . . . . . . . . . . . . . . 1–1 Tradeoffs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 Guidelines for Using Tightly Coupled Memory . . . .. . . . . . . . 1–2 Hardware Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Software Guidelines  . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 1–3 Locating Functions in Tightly Coupled Memory  . . . . . . . . . . . . . 1–3 Tightly Coupled Memory Interface   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 Restrictions   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 Dual Port Memories  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . 1–5 Building a Nios II System with Tightly Coupled Memory  . . . . . . . . . . . 1–5

    標簽: Nios 耦合 存儲器 教程

    上傳時間: 2013-10-13

    上傳用戶:黃婷婷思密達

  • Employing a Single-Chip Transceiver in Femtocell Base-Station Applications

    Abstract: This application note discusses the development and deployment of 3G cellular femtocell base stations. The technicalchallenges for last-mile residential connectivity and adding system capacity in dense urban environments are discussed, with 3Gfemtocell base stations as a cost-effective solution. Maxim's 3GPP TS25.104-compliant transceiver solution is presented along withcomplete radio reference designs such as RD2550. For more information on the RD2550, see reference design 5364, "FemtocellRadio Reference Designs Using the MAX2550–MAX2553 Transceivers."

    標簽: Base-Station Applications Single-Chip Transceiver

    上傳時間: 2013-11-05

    上傳用戶:超凡大師

  • XAPP098 - Spartan FPGA低成本、高效率串行配置

    This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration circuitry. As a result, neither processor nor PROM needs to be fullydedicated to performing Spartan configuration.In particular, information is provided on how the idle processing time of an on-board controller can be used to loadconfiguration data from an off-board source. As a result, it is possible to upgrade a Spartan design in the field by sending thebitstream over a network.

    標簽: Spartan XAPP FPGA 098

    上傳時間: 2013-11-01

    上傳用戶:wojiaohs

  • XAPP806 -決定DDR反饋時鐘的最佳DCM相移

    This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.

    標簽: XAPP 806 DDR DCM

    上傳時間: 2014-11-26

    上傳用戶:erkuizhang

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