The WCDMA Physical Layer Demo consists of an end-to-end (transmitter-to-receiver) simulation of the Frequency Division Duplex (FDD) Downlink physical layer for several Dedicated Channels (DCH) as specified by the 3GPP standard (Release 99).
標簽： transmitter-to-receiver end-to-end simulation Physical
上傳時間： 2013-11-28
上傳用戶：gdgzhym
MSP-FET430P410 Demo - Timer_A Toggle P5.1, CCR0 Contmode ISR, DCO SMCLK Description Toggle P5.1 using using software and TA_0 ISR. Toggle rate is set at 50000 DCO/SMCLK cycles. Default DCO frequency used for TACLK. Durring the TA_0 ISR P5.1 is toggled and 50000 clock cycles are added to CCR0. TA_0 ISR is triggered exactly 50000 cycles. CPU is normally off and used only durring TA_ISR. ACLK = n/a, MCLK = SMCLK = TACLK = DCO ~ 800k
標簽： Toggle Description 5.1 Contmode
上傳時間： 2014-01-04
上傳用戶：gut1234567
The purpose of this document is to present how to use the Timer for the generation of a PWM signal tunable in frequency and duty cycle. As an application example, this document is based on a basic “music” synthesizer through an external buzzer. Example code is also available in the it.
標簽： generation the document purpose
上傳時間： 2013-12-20
上傳用戶：z754970244
非平穩信號分析之時頻分析工具箱，附加使用說明文檔。Time-Frequency toolbox, with reference guide.
上傳時間： 2016-09-07
上傳用戶：電子世界
Circular Convolution of two equal-length vectors. Highlights that circular convolution in the time domain is the effectively the same as element-by-element multiplication in the frequency domain.
標簽： equal-length Convolution convolution Highlights
上傳時間： 2014-01-22
上傳用戶：aig85
WB_BPSK_Analysis.rar:BPSK modulation and link analysis of UWB monocycle and doublet waveforms.Revised 1/2/05-JC.This m file plots the time and frequency waveforms for BPSK 1st and 2nd derivative equations used in UWB system analysis.
標簽： WB_BPSK_Analysis modulation and monocycle
上傳時間： 2016-11-12
上傳用戶：邶刖
script for generting transmit waveforms in a minimum shift keying, a form of continuous phase frequency shift keying
標簽： continuous generting waveforms transmit
上傳時間： 2016-11-30
上傳用戶：ANRAN
MATLAB Code for Optimal Quincunx Filter Bank Design Yi Chen July 17, 2006 This file introduces the MATLAB code that implements the two algorithms (i.e., Algorithms 1 and 2 in [1], or Algorithms 4.1 and 4.2 in [2]) used for the construction of quincunx filter banks with perfect reconstruction, linear phase, high coding gain, certain vanishing moments properties, and good frequency selectivity. The code can be used to design quincunx filter banks with two, three, or four lifting steps. The SeDuMi Matlab toolbox [3] is used to solve the second-order cone programming subproblems in the two algorithms, and must be installed in order for this code to work.
標簽： introduces Quincunx Optimal MATLAB
上傳時間： 2014-01-15
上傳用戶：cc1
DDR SDRAM控制器的VHDL源代碼，含詳細設計文檔。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.
上傳時間： 2014-11-01
上傳用戶：l254587896
*** *** *** *** *** *** ***** ** Two wire/I2C Bus READ/WRITE Sample Routines of Microchip s ** 24Cxx / 85Cxx serial CMOS EEPROM interfacing to a ** PIC16C54 8-bit CMOS single chip microcomputer ** Revsied Version 2.0 (4/2/92). ** ** Part use = PIC16C54-XT/JW ** Note: 1) All timings are based on a reference crystal frequency of 2MHz ** which is equivalent to an instruction cycle time of 2 usec. ** 2) Address and literal values are read in octal unless otherwise ** specified.
標簽： Microchip Routines Sample WRITE
上傳時間： 2013-12-27
上傳用戶：ljmwh2000
