A new PLL topology and a new simplified linear model are presented. The new fractional-N synthesizer presents no reference spurs and lowers the overall phase noise, thanks to the presence of a SampleJHold block. With a new simulation methodology it is possible to perform very accurate simulations, whose results match closely those obtained with the linear PLL model developed.
This paper presents the key circuits of a 1MHz bandwidth, 750kb/s GMSK transmitter. The fractional-N synthesizer forming the basis of the transmitter uses a combined phasefrequency
detector (PFD) and digital-to-analog converter (DAC) circuit element to obtain >28dB high frequency noise reduction when compared to classicalfrequency synthesis.
FRFT時頻變換代碼（參考算法：H.M. Ozaktas, M.A. Kutay, and G. Bozdagi.Digital computation of the fractional Fourier transform.IEEE Trans. Sig. Proc., 44:2141--2150, 1996.）
