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  • 基于ZigBee技術(shù)的無(wú)線智能家用燃?xì)鈭?bào)警系統(tǒng)

    在研究傳統(tǒng)家用燃?xì)鈭?bào)警器的基礎(chǔ)上,以ZigBee協(xié)議為平臺(tái),構(gòu)建mesh網(wǎng)狀網(wǎng)絡(luò)實(shí)現(xiàn)網(wǎng)絡(luò)化的智能語(yǔ)音報(bào)警系統(tǒng)。由于傳感器本身的溫度和實(shí)際環(huán)境溫度的影響,傳感器標(biāo)定后采用軟件補(bǔ)償方法。為了減少系統(tǒng)費(fèi)用,前端節(jié)點(diǎn)采用半功能節(jié)點(diǎn)設(shè)備,路由器和協(xié)調(diào)器采用全功能節(jié)點(diǎn)設(shè)備,構(gòu)建mesh網(wǎng)絡(luò)所形成的家庭內(nèi)部報(bào)警系統(tǒng),通過(guò)通用的電話接口連接到外部的公用電話網(wǎng)絡(luò),啟動(dòng)語(yǔ)音模塊進(jìn)行報(bào)警。實(shí)驗(yàn)結(jié)果表明,在2.4 GHz頻率下傳輸,有墻等障礙物的情況下,節(jié)點(diǎn)的傳輸距離大約為35 m,能夠滿足家庭需要,且系統(tǒng)工作穩(wěn)定,但在功耗方面仍需進(jìn)一步改善。 Abstract:  On the basis of studying traditional household gas alarm system, this paper proposed the platform for the ZigBee protocol,and constructed mesh network to achieve network-based intelligent voice alarm system. Because of the sensor temperature and the actual environment temperature, this system design used software compensation after calibrating sensor. In order to reduce system cost, semi-functional node devices were used as front-end node, however, full-function devices were used as routers and coordinator,constructed alarm system within the family by building mesh network,connected to the external public telephone network through the common telephone interface, started the voice alarm module. The results indicate that nodes transmit about 35m in the distance in case of walls and other obstacles by 2.4GHz frequency transmission, this is able to meet family needs and work steadily, but still needs further improvement in power consumption.

    標(biāo)簽: ZigBee 無(wú)線智能 報(bào)警系統(tǒng)

    上傳時(shí)間: 2013-10-30

    上傳用戶:swaylong

  • XAPP122 - Spartan-XL FPGA的Express配置

    Express Mode uses an 8-bit wide bus path for fast configuration of Xilinx FPGAs. Thisapplication note provides information on how to perform Express configuration specifically forthe Spartan™-XL family. The Express mode signals and their associated timing are defined.The steps of Express configuration are described in detail, followed by detailed instructions thatshow how to implement the configuration circui

    標(biāo)簽: Spartan-XL Express XAPP FPGA

    上傳時(shí)間: 2015-01-02

    上傳用戶:nanxia

  • WP264-在數(shù)字視頻應(yīng)用中使用CPLD

      The CoolRunner-II CPLD is a highly uniform family of fast, low-power devices. Theunderlying architecture is a traditional CPLD architecture, combining macrocells intofunction blocks interconnected with a global routing matrix, the Xilinx AdvancedInterconnect Matrix (AIM). The function blocks use a PLA configuration that allowsall product terms to be routed and shared among any of the macrocells of the functionblock.

    標(biāo)簽: CPLD 264 WP 數(shù)字

    上傳時(shí)間: 2013-11-03

    上傳用戶:1037540470

  • AN26與LTC1090的接口設(shè)計(jì)

    A collection of interface applications between various microprocessors/ controllers and the LTC1090 family of data acquisition systems. The note is divided into sections specific to each interface.

    標(biāo)簽: 1090 LTC AN 26

    上傳時(shí)間: 2013-11-08

    上傳用戶:sssnaxie

  • ... Samsung’s ARM 900 S3C2440 Specs. Tech NewsSamsung Semiconductor, Inc. Source: Convergence Promot

    ... Samsung’s ARM 900 S3C2440 Specs. Tech NewsSamsung Semiconductor, Inc. Source: Convergence Promotions Mobile Applications ... Samsung’s S3C2440 is the industry’s fastest ARM9? family core-based application processor. With an advanced CPU Core

    標(biāo)簽: Semiconductor NewsSamsung Convergence Samsung

    上傳時(shí)間: 2014-01-25

    上傳用戶:ljmwh2000

  • 關(guān)于FPGA流水線設(shè)計(jì)的論文 This work investigates the use of very deep pipelines for implementing circuits in

    關(guān)于FPGA流水線設(shè)計(jì)的論文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.

    標(biāo)簽: investigates implementing pipelines circuits

    上傳時(shí)間: 2015-07-26

    上傳用戶:CHINA526

  • 一個(gè)簡(jiǎn)單的SPI IP核

    一個(gè)簡(jiǎn)單的SPI IP核,SPI Core Specifications 可以從說(shuō)明文檔中找到! The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchronous communication protocol that requires a minimum of 3 wires. FEATURES: · Compatible with Motorola’s SPI specifications · Enhanced M68HC11 Serial Peripheral Interface · 4 entries deep read FIFO · 4 entries deep write FIFO · Interrupt generation after 1, 2, 3, or 4 transferred bytes · 8 bit WISHBONE RevB.3 Classic interface · Operates from a wide range of input clock frequencies · Static synchronous design · Fully synthesizable

    標(biāo)簽:

    上傳時(shí)間: 2015-09-17

    上傳用戶:TRIFCT

  • RTX-51 is a runtime library that, together with C51, allows real-time systems to be implemented for

    RTX-51 is a runtime library that, together with C51, allows real-time systems to be implemented for all processors of the 8051 family (e.g., 8051, 8052, 80515, etc.), except for the 8?C751 and 8?C752. RTX-251 extends the functionality of the RTX-51 to the new intel MCSÒ 251 family of processors. It is available as a set of runtime libraries supporting the binary and the source mode to be used with the C251.

    標(biāo)簽: implemented real-time together runtime

    上傳時(shí)間: 2013-12-13

    上傳用戶:refent

  • This collection of routines allows the Atmel AT89C5x and AT89Cx051 micro- controllers to read and w

    This collection of routines allows the Atmel AT89C5x and AT89Cx051 micro- controllers to read and write the AT25xxx family of serial CMOS EEPROMS.

    標(biāo)簽: controllers collection and routines

    上傳時(shí)間: 2015-10-19

    上傳用戶:gundan

  • This document is an operation guide for the MPC8XXFADS board. It contains operational, functional a

    This document is an operation guide for the MPC8XXFADS board. It contains operational, functional and general information about the FADS. The MPC8XXFADS is meant to serve as a platform for s/ w and h/w development around the MPC8XX family processors. Using its on-board resources and its associated debugger, a developer is able to download his code, run it, set breakpoints, display memory and registers and connect his own proprietary h/w via the expansion connectors, to be incorporated to a desired system with the MPC8XX processor.

    標(biāo)簽: operational MPC8XXFADS functional operation

    上傳時(shí)間: 2014-03-10

    上傳用戶:zsjinju

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