The PCA9671 provides general purpose remote I/O expansion for most microcontrollerfamilies via the two-line bidirectional bus (I2C-bus) and is a part of the Fast-mode Plus(Fm+) family.The PCA9671 is a drop in upgrade for the PCF8575 providing higher I2C-bus speeds(1 MHz versus 400 kHz) so that the output can support PWM dimming of LEDs, higherI2C-bus drive (30 mA versus 3 mA) so that many more devices can be on the bus withoutthe need for bus buffers, higher total package sink capacity (400 mA versus 100 mA) thatsupports having all 25 mA LEDs on at the same time and more device addresses (64versus 8) to allow many more devices on the bus without address conflicts.
上傳時間： 2013-10-12
上傳用戶：laomv123
The PCA9672 provides general purpose remote I/O expansion for most microcontrollerfamilies via the two-line bidirectional bus (I2C-bus) and is a part of the Fast-mode Plusfamily.The PCA9672 is a drop-in upgrade for the PCF8574 providing higher Fast-mode Plus(Fm+) I2C-bus speeds (1 MHz versus 400 kHz) so that the output can support PWMdimming of LEDs, higher I2C-bus drive (30 mA versus 3 mA) so that many more devicescan be on the bus without the need for bus buffers, higher total package sink capacity(200 mA versus 100 mA) that supports having all LEDs on at the same time and moredevice addresses (16 versus 8) are available to allow many more devices on the buswithout address conflicts.
上傳時間： 2013-10-23
上傳用戶：jasonheung
The PCA9673 provides general purpose remote I/O expansion for most microcontrollerfamilies via the two-line bidirectional bus (I2C-bus) and is a part of the Fast-mode Plusfamily.The PCA9673 is a drop in upgrade for the PCF8575 providing higher Fast-mode Plus(Fm+) I2C-bus speeds (1 MHz versus 400 kHz) so that the output can support PWMdimming of LEDs, higher I2C-bus drive (30 mA versus 3 mA) so that many more devicescan be on the bus without the need for bus buffers, higher total package sink capacity(400 mA versus 100 mA) that supports having all 25 mA LEDs on at the same time andmore device addresses (16 versus 8) are available to allow many more devices on the buswithout address conflicts.
上傳時間： 2013-10-29
上傳用戶：wkchong
Luminary Micro provides an analog-to-digital converter (ADC) module on some members of theStellaris microcontroller family. The hardware resolution of the ADC is 10 bits; however, due to noiseand other accuracy-diminishing factors, the true accuracy is less than 10 bits. This application noteprovides a software-based oversampling technique, resulting in an improved Effective Number OfBits (ENOB) in the conversion result. This document describes methods of oversampling an inputsignal, and the impact on precision and overall system performance.
標簽： Oversampling Techniques ADC fo
上傳時間： 2013-12-17
上傳用戶：zhyiroy
The Philips family of Multiplexers and Switches consists of bi-directional translating switches controlled via the I2C or SMBus to fan out an upstream SCL/SDA pair to 2, 4 or 8 downstream channels of SCx/SDx pairs. The Multiplexers allow only one downstream channel to be selected at a time, while the Switches allow any individual downstream channel or combination of downstream channels to be selected, depending on the content of the programmable control register. Once one or several channels have been selected, the device acts as a wire, allowing the master on the upstream channel to send commands to devices on all the active downstream channels, and devices on the active downstream channels to communicate with each other and the master. External pull-up resistors are used to pull each individual channel up to the desired voltage level. Combined interrupt output and hardware reset input are device options that are featured.
上傳時間： 2013-10-11
上傳用戶：dianxin61
PCA9511, PCA9512, PCA9513, PCA9514, PCA9515, PCA9516, PCA9518,P82B96, P82B715Abstract - Philips Semiconductors family of Repeaters, Hubs and Expanders are detailed in this application notethat discusses device operation, maximum cable length and frequency calculations and typical applications.
上傳時間： 2013-11-21
上傳用戶：wlcaption
MSP430系列超低功耗16位單片機原理與應用TI公司的MSP430系列微控制器是一個近期推出的單片機品種。它在超低功耗和功能集成上都有一定的特色，尤其適合應用在自動信號采集系統(tǒng)、液晶顯示智能化儀器、電池供電便攜式裝置、超長時間連續(xù)工作設備等領(lǐng)域。《MSP430系列超低功耗16位單片機原理與應用》對這一系列產(chǎn)品的原理、結(jié)構(gòu)及內(nèi)部各功能模塊作了詳細的說明，并以方便工程師及程序員使用的方式提供軟件和硬件資料。由于MSP430系列的各個不同型號基本上是這些功能模塊的不同組合，因此，掌握《MSP430系列超低功耗16位單片機原理與應用》的內(nèi)容對于MSP430系列的原理理解和應用開發(fā)都有較大的幫助。《MSP430系列超低功耗16位單片機原理與應用》的內(nèi)容主要根據(jù)TI公司的《MSP430 family Architecture Guide and Module Library》一書及其他相關(guān)技術(shù)資料編寫。 《MSP430系列超低功耗16位單片機原理與應用》供高等院校自動化、計算機、電子等專業(yè)的教學參考及工程技術(shù)人員的實用參考，亦可做為應用技術(shù)的培訓教材。MSP430系列超低功耗16位單片機原理與應用 目錄 第1章 MSP430系列1.1 特性與功能1.2 系統(tǒng)關(guān)鍵特性1.3 MSP430系列的各種型號??第2章 結(jié)構(gòu)概述2.1 CPU2.2 代碼存儲器?2.3 數(shù)據(jù)存儲器2.4 運行控制?2.5 外圍模塊2.6 振蕩器、倍頻器和時鐘發(fā)生器??第3章 系統(tǒng)復位、中斷和工作模式?3.1 系統(tǒng)復位和初始化3.2 中斷系統(tǒng)結(jié)構(gòu)3.3 中斷處理3.3.1 SFR中的中斷控制位3.3.2 外部中斷3.4 工作模式3.5 低功耗模式3.5.1 低功耗模式0和模式13.5.2 低功耗模式2和模式33.5.3 低功耗模式43.6 低功耗應用要點??第4章 存儲器組織4.1 存儲器中的數(shù)據(jù)4.2 片內(nèi)ROM組織4.2.1 ROM表的處理4.2.2 計算分支跳轉(zhuǎn)和子程序調(diào)用4.3 RAM與外圍模塊組織4.3.1 RAM4.3.2 外圍模塊--地址定位4.3.3 外圍模塊--SFR??第5章 16位CPU?5.1 CPU寄存器5.1.1 程序計數(shù)器PC5.1.2 系統(tǒng)堆棧指針SP5.1.3 狀態(tài)寄存器SR5.1.4 常數(shù)發(fā)生寄存器CG1和CG2?5.2 尋址模式5.2.1 寄存器模式5.2.2 變址模式5.2.3 符號模式5.2.4 絕對模式5.2.5 間接模式5.2.6 間接增量模式5.2.7 立即模式5.2.8 指令的時鐘周期與長度5.3 指令集概述5.3.1 雙操作數(shù)指令5.3.2 單操作數(shù)指令5.3.3 條件跳轉(zhuǎn)5.3.4 模擬指令的簡短格式5.3.5 其他指令5.4 指令分布??第6章 硬件乘法器?6.1 硬件乘法器的操作6.2 硬件乘法器的寄存器6.3 硬件乘法器的SFR位6.4 硬件乘法器的軟件限制6.4.1 硬件乘法器的軟件限制--尋址模式6.4.2 硬件乘法器的軟件限制--中斷程序??第7章 振蕩器與系統(tǒng)時鐘發(fā)生器?7.1 晶體振蕩器7.2 處理機時鐘發(fā)生器7.3 系統(tǒng)時鐘工作模式7.4 系統(tǒng)時鐘控制寄存器7.4.1 模塊寄存器7.4.2 與系統(tǒng)時鐘發(fā)生器相關(guān)的SFR位7.5 DCO典型特性??第8章 數(shù)字I/O配置?8.1 通用端口P08.1.1 P0的控制寄存器8.1.2 P0的原理圖8.1.3 P0的中斷控制功能8.2 通用端口P1、P28.2.1 P1、P2的控制寄存器8.2.2 P1、P2的原理圖8.2.3 P1、P2的中斷控制功能8.3 通用端口P3、P48.3.1 P3、P4的控制寄存器8.3.2 P3、P4的原理圖8.4 LCD端口8.5 LCD端口--定時器/端口比較器??第9章 通用定時器/端口模塊?9.1 定時器/端口模塊操作9.1.1 定時器/端口計數(shù)器TPCNT1--8位操作9.1.2 定時器/端口計數(shù)器TPCNT2--8位操作9.1.3 定時器/端口計數(shù)器--16位操作9.2 定時器/端口寄存器9.3 定時器/端口SFR位9.4 定時器/端口在A/D中的應用9.4.1 R/D轉(zhuǎn)換原理9.4.2 分辨率高于8位的轉(zhuǎn)換??第10章 定時器?10.1 Basic Timer110.1.1 Basic Timer1寄存器10.1.2 SFR位10.1.3 Basic Timer1的操作10.1.4 Basic Timer1的操作--LCD時鐘信號fLCD?10.2 8位間隔定時器/計數(shù)器10.2.1 8位定時器/計數(shù)器的操作10.2.2 8位定時器/計數(shù)器的寄存器10.2.3 與8位定時器/計數(shù)器有關(guān)的SFR位10.2.4 8位定時器/計數(shù)器在UART中的應用10.3 看門狗定時器11.1.3 比較模式11.1.4 輸出單元11.2 TimerA的寄存器11.2.1 TimerA控制寄存器TACTL11.2.2 捕獲/比較控制寄存器CCTL11.2.3 TimerA中斷向量寄存器11.3 TimerA的應用11.3.1 TimerA增計數(shù)模式應用11.3.2 TimerA連續(xù)模式應用11.3.3 TimerA增/減計數(shù)模式應用11.3.4 TimerA軟件捕獲應用11.3.5 TimerA處理異步串行通信協(xié)議11.4 TimerA的特殊情況11.4.1 CCR0用做周期寄存器11.4.2 定時器寄存器的啟/停11.4.3 輸出單元Unit0??第12章 USART外圍接口--UART模式?12.1 異步操作12.1.1 異步幀格式12.1.2 異步通信的波特率發(fā)生器12.1.3 異步通信格式12.1.4 線路空閑多處理機模式12.1.5 地址位格式12.2 中斷與控制功能12.2.1 USART接收允許12.2.2 USART發(fā)送允許12.2.3 USART接收中斷操作12.2.4 USART發(fā)送中斷操作12.3 控制與狀態(tài)寄存器12.3.1 USART控制寄存器UCTL12.3.2 發(fā)送控制寄存器UTCTL12.3.3 接收控制寄存器URCTL12.3.4 波特率選擇和調(diào)制控制寄存器12.3.5 USART接收數(shù)據(jù)緩存URXBUF12.3.6 USART發(fā)送數(shù)據(jù)緩存UTXBUF12.4 UART模式--低功耗模式應用特性12.4.1 由UART幀啟動接收操作12.4.2 時鐘頻率的充分利用與UART模式的波特率12.4.3 節(jié)約MSP430資源的多處理機模式12.5 波特率的計算??第13章 USART外圍接口--SPI模式?13.1 USART的同步操作13.1.1 SPI模式中的主模式--MM=1、SYNC=113.1.2 SPI模式中的從模式--MM=0、SYNC=113.2 中斷與控制功能13.2.1 USART接收允許13.2.2 USART發(fā)送允許13.2.3 USART接收中斷操作13.2.4 USART發(fā)送中斷操作13.3 控制與狀態(tài)寄存器13.3.1 USART控制寄存器13.3.2 發(fā)送控制寄存器UTCTL13.3.3 接收控制寄存器URCTL13.3.4 波特率選擇和調(diào)制控制寄存器13.3.5 USART接收數(shù)據(jù)緩存URXBUF13.3.6 USART發(fā)送數(shù)據(jù)緩存UTXBUF??第14章 液晶顯示驅(qū)動?14.1 LCD驅(qū)動基本原理14.2 LCD控制器/驅(qū)動器14.2.1 LCD控制器/驅(qū)動器功能14.2.2 LCD控制與模式寄存器14.2.3 LCD顯示內(nèi)存14.2.4 LCD操作軟件例程14.3 LCD端口功能14.4 LCD與端口模式混合應用實例??第15章 A/D轉(zhuǎn)換器?15.1 概述15.2 A/D轉(zhuǎn)換操作15.2.1 A/D轉(zhuǎn)換15.2.2 A/D中斷15.2.3 A/D量程15.2.4 A/D電流源15.2.5 A/D輸入端與多路切換15.2.6 A/D接地與降噪15.2.7 A/D輸入與輸出引腳15.3 A/D控制寄存器??第16章 其他模塊16.1 晶體振蕩器16.2 上電電路16.3 晶振緩沖輸出??附錄A 外圍模塊地址分配?附錄B 指令集描述?B1 指令匯總B2 指令格式B3 不增加ROM開銷的指令模擬B4 指令說明B5 用幾條指令模擬的宏指令??附錄C EPROM編程?C1 EPROM操作C2 快速編程算法C3 通過串行數(shù)據(jù)鏈路應用\"JTAG\"特性的EPROM模塊編程C4 通過微控制器軟件實現(xiàn)對EPROM模塊編程??附錄D MSP430系列單片機參數(shù)表?附錄E MSP430系列單片機產(chǎn)品編碼?附錄F MSP430系列單片機封裝形式?
上傳時間： 2014-05-07
上傳用戶：lwq11
The C500 microcontroller family usually provides only one on-chip synchronous serialchannel (SSC). If a second SSC is required, an emulation of the missing interface mayhelp to avoid an external hardware solution with additional electronic components.The solution presented in this paper and in the attached source files emulates the mostimportant SSC functions by using optimized SW routines with a performance up to 25KBaud in Slave Mode with half duplex transmission and an overhead less than 60% atSAB C513 with 12 MHz. Due to the implementation in C this performance is not the limitof the chip. A pure implementation in assembler will result in a strong reduction of theCPU load and therefore increase the maximum speed of the interface. In addition,microcontrollers like the SAB C505 will speed up the interface by a factor of two becauseof an optimized architecture compared with the SAB C513.Moreover, this solution lays stress on using as few on-chip hardware resources aspossible. A more excessive consumption of those resources will result in a highermaximum speed of the emulated interface.Due to the restricted performance of an 8 bit microcontroller a pin compatible solution isprovided only; the internal register based programming interface is replaced by a set ofsubroutine calls.The attached source files also contain a test shell, which demonstrates how to exchangeinformation between an on-chip HW-SSC and the emulated SW-SSC via 5 external wiresin different operation modes. It is based on the SAB C513 (Siemens 8 bit microcontroller).A table with load measurements is presented to give an indication for the fraction of CPUperformance required by software for emulating the SSC.
標簽： synchronous Emulating serial
上傳時間： 2014-01-31
上傳用戶：z1191176801
In this document, the term Ô60xÕ is used to denote a 32-bit microprocessor from the PowerPC architecture family that conforms to the bus interface of the PowerPC 601ª, PowerPC 603ª, or PowerPC 604 microprocessors. Note that this does not include the PowerPC 602ª microprocessor which has a multiplexed address/data bus. 60x processors implement the PowerPC architecture as it is speciÞed for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits,and ßoating-point data types of 32 and 64 bits (single-precision and double-precision).1.1 Overview The MPC106 provides an integrated high-bandwidth, high-performance, TTL-compatible interface between a 60x processor, a secondary (L2) cache or additional (up to four total) 60x processors, the PCI bus,and main memory. This section provides a block diagram showing the major functional units of the 106 and describes brießy how those units interact.Figure 1 shows the major functional units within the 106. Note that this is a conceptual block diagram intended to show the basic features rather than an attempt to show how these features are physically implemented on the device.
上傳時間： 2013-10-08
上傳用戶：18711024007
The Motorola MPC106 PCI bridge/memory controller provides a PowerPCªmicroprocessor common hardware reference platform (CHRPª) compliant bridgebetween the PowerPC microprocessor family and the Peripheral Component Interconnect(PCI) bus. In this document, the term Ô106Õ is used as an abbreviation for the phraseÔMPC106 PCI bridge/memory controllerÕ. This document contains pertinent physicalcharacteristics of the 106. For functional characteristics refer to theMPC106 PCI Bridge/Memory Controller UserÕs Manual.This document contains the following topics:Topic PageSection 1.1, ÒOverviewÓ 2Section 1.2, ÒFeaturesÓ 3Section 1.3, ÒGeneral ParametersÓ 5Section 1.4, ÒElectrical and Thermal CharacteristicsÓ 5Section 1.5, ÒPin AssignmentsÓ 17Section 1.6, ÒPinout Listings 18Section 1.7, ÒPackage DescriptionÓ 22Section 1.8, ÒSystem Design InformationÓ 24Section 1.9, ÒDocument Revision HistoryÓ 29Section 1.10, ÒOrdering InformationÓ 29
上傳時間： 2013-11-04
上傳用戶：as275944189
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