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electrostatic

  • TION ESD (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 V readil

    TION ESD (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. WARNING! Although the AD7008 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

    標簽: electrostatic electrostatic discharge sensitive

    上傳時間: 2014-01-12

    上傳用戶:2467478207

  • electrostatic Discharge Protection

    electrostatic discharge (ESD) is one of the most prevalent threats to the reliability of electronic components. It is an event in which a finite amount of charge is trans- ferred from one object (i.e., human body) to another (i.e., microchip). This process can result in a very high current passing through the microchip within a very short period of time, and, hence, more than 35% of chip damages can be attributed to an ESD-related event. As such, designing on-chip ESD structures to protect integrated circuits against the ESD stresses is a high priority in the semiconductor industry.

    標簽: electrostatic Protection Discharge

    上傳時間: 2020-06-05

    上傳用戶:shancjb

  • Construction Strategy of ESD P

    Construction Strategy of ESD Protection CircuitAbstract: The principles used to construct ESD protection on circuits and the basic conceptions of ESD protection design are presented.Key words:ESD protection/On circuit, ESD design window, ESD current path1 引言靜電放電(ESD,electrostatic Discharge)給電子器件環境會帶來破壞性的后果。它是造成集成電路失效的主要原因之一。隨著集成電路工藝不斷發展,互補金屬氧化物半導體(CMOS,Complementary Metal-Oxide Semiconductor)的特征尺寸不斷縮小,金屬氧化物半導體(MOS, Metal-Oxide Semiconductor)的柵氧厚度越來越薄,MOS 管能承受的電流和電壓也越來越小,因此要進一步優化電路的抗ESD 性能,需要從全芯片ESD 保護結構的設計來進行考慮。

    標簽: Construction Strategy ESD of

    上傳時間: 2013-11-09

    上傳用戶:Aidane

  • Design of a MEMS micromirror actuated by electrostatic repulsive force

    mems

    標簽: electrostatic micromirror repulsive actuated

    上傳時間: 2013-10-18

    上傳用戶:manking0408

  • MAX338/MAX339的英文數據手冊

      本軟件是關于MAX338, MAX339的英文數據手冊:MAX338, MAX339   8通道/雙4通道、低泄漏、CMOS模擬多路復用器   The MAX338/MAX339 are monolithic, CMOS analog multiplexers (muxes). The 8-channel MAX338 is designed to connect one of eight inputs to a common output by control of a 3-bit binary address. The dual, 4-channel MAX339 is designed to connect one of four inputs to a common output by control of a 2-bit binary address. Both devices can be used as either a mux or a demux. On-resistance is 400Ω max, and the devices conduct current equally well in both directions.   These muxes feature extremely low off leakages (less than 20pA at +25°C), and extremely low on-channel leakages (less than 50pA at +25°C). The new design offers guaranteed low charge injection (1.5pC typ) and electrostatic discharge (ESD) protection greater than 2000V, per method 3015.7. These improved muxes are pin-compatible upgrades for the industry-standard DG508A and DG509A. For similar Maxim devices with lower leakage and charge injection but higher on-resistance, see the MAX328 and MAX329.

    標簽: MAX 338 339 英文

    上傳時間: 2013-11-12

    上傳用戶:18711024007

  • The MAX481E, MAX483E, MAX485E, MAX487E–MAX491E, and MAX1487E are low-power transceivers for RS-485

    The MAX481E, MAX483E, MAX485E, MAX487E–MAX491E, and MAX1487E are low-power transceivers for RS-485 and RS-422 communications in harsh environments. Each driver output and receiver input is protected against ±15kV electrostatic discharge (ESD) shocks, without latchup. These parts contain one driver and one receiver. The MAX483E, MAX487E, MAX488E, and MAX489E feature reduced slewrate drivers that minimize EMI and reduce reflections caused by improperly terminated cables, thus allowing error-free data transmission up to 250kbps. The driver slew rates of the MAX481E, MAX485E, MAX490E, MAX491E, and MAX1487E are not limited, allowing them to transmit up to 2.5Mbps.

    標簽: MAX transceivers 485 low-power

    上傳時間: 2013-12-22

    上傳用戶:小寶愛考拉

  • Basic+ESD+and+IO+Design

    This effort started as an answer to the numerous questions the authors have repeatedly had to answer about electrostatic discharge (ESD) protection and input/output (1/0) designs. In the past no comprehensive book existed suffi- ciently covering these areas, and these topics were rarely taught in engineering schools. Thus first-time I/O and ESD protection designers have had consider- able trouble getting started. This book is in part an answer to such needs.

    標簽: Design Basic ESD and IO

    上傳時間: 2020-06-05

    上傳用戶:shancjb

  • Contamination+and+ESD+Control

    Contamination and electrostatic discharge (ESD) are now becoming recognized as factors affecting yield and reliability in an ever-increasing number of industries. Whereas contam- ination traditionally was recognized as affecting the semiconductor, disk drive, aerospace, pharmaceutical, and medical device industries, today such industries as automobile and food production are also discovering the benefits of contamination control. ESD control has experienced a similar growth in applications.

    標簽: Contamination Control and ESD

    上傳時間: 2020-06-05

    上傳用戶:shancjb

  • ESD - Circuits and Devices

    electrostatic discharge (ESD) phenomena have been known to mankind since the Greek Empire when Thales of Miletus, one of the Seven Sages of Greece, noticed the attraction of strands of hay to amber, leading to the coining of the word ‘‘electron.’’ In the 17th century, Gilbert and Cabeo addressed the attractive and repulsive nature of electricity. In the 18th century, a rapid increase of interest occurred for scientists in the understanding of electrical physics—Gray, du Fay, Nollet, Musschenbroeck, Franklin, Watson, Aepinus, Canton,

    標簽: Circuits Devices ESD and

    上傳時間: 2020-06-05

    上傳用戶:shancjb

  • ESD - Failure Mechanisms and Models

    Failure analysis is invaluable in the learning process of electrostatic discharge (ESD) and electrical overstress (EOS) protection design and development [1–8]. In the failure analysis of EOS, ESD, and latchup events, there are a number of unique failure analysis processes andinformationthatcanprovidesignificantunderstandingandillumination[4].Today,thereis still no design methodology or computer-aided design (CAD) tool which will predict EOS, ESDprotectionlevels,andlatchupinasemiconductorchip;thisisoneofthesignificantreasons why failure analysis is critical to the ESD design discipline.

    標簽: Mechanisms Failure Models ESD and

    上傳時間: 2020-06-05

    上傳用戶:shancjb

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