學(xué)習(xí)FPGA的課件，內(nèi)容含有軟件的介紹，Altera和Xilinx芯片的介紹，以及VHDL的編程風(fēng)格。和一些實(shí)例講解。
上傳時(shí)間： 2013-10-15
上傳用戶：xmsmh
首先得掌握FPGA的芯片結(jié)構(gòu)
標(biāo)簽： FPGA 基本結(jié)構(gòu)
上傳時(shí)間： 2013-12-29
上傳用戶：yph853211
This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration circuitry. As a result, neither processor nor PROM needs to be fullydedicated to performing Spartan configuration.In particular, information is provided on how the idle processing time of an on-board controller can be used to loadconfiguration data from an off-board source. As a result, it is possible to upgrade a Spartan design in the field by sending thebitstream over a network.
標(biāo)簽： Spartan XAPP FPGA 098
上傳時(shí)間： 2014-08-16
上傳用戶：adada
LMS自適應(yīng)濾波器是一種廣泛使用的數(shù)字信號(hào)處理算法，對(duì)其實(shí)現(xiàn)有多種方法．通過(guò)研究其特性的基礎(chǔ)上，提出了在FPGA 中使用軟處理的嵌入式實(shí)現(xiàn)方案，文中對(duì)實(shí)現(xiàn)方式的優(yōu)缺點(diǎn)進(jìn)行了分析，并給出了硬件實(shí)現(xiàn)中的有線字長(zhǎng)效應(yīng)進(jìn)行了詳細(xì)的分析．
標(biāo)簽： FPGA LMS 自適應(yīng)濾波器
上傳時(shí)間： 2014-01-21
上傳用戶：gokk
在點(diǎn)對(duì)多點(diǎn)主從通信系統(tǒng)中,需要合適的接口形式和通信協(xié)議實(shí)現(xiàn)主站與各從站的信息交換。RS -485 接口是適合這種需求的一種標(biāo)準(zhǔn)接口形式。當(dāng)選擇主從多點(diǎn)同步通信方式時(shí),工作過(guò)程與幀格式符合HDLC/SDLC協(xié)議。介紹了采用VHDL 語(yǔ)言在FPGA 上實(shí)現(xiàn)的以HDLC/ SDLC 協(xié)議控制為基礎(chǔ)的RS - 485 通信接口芯片。實(shí)驗(yàn)表明,這種接口芯片操作簡(jiǎn)單、體積小、功耗低、可靠性高,極具實(shí)用價(jià)值。
上傳時(shí)間： 2013-11-02
上傳用戶：zhf01y
介紹了HDLC協(xié)議RS485總線控制器的FPGA實(shí)現(xiàn)
上傳時(shí)間： 2013-11-04
上傳用戶：heart_2007
本白皮書(shū)主要介紹 Spartan®-6 FPGA 如何滿足大批量系統(tǒng)的需求。包括經(jīng)濟(jì)高效地驅(qū)動(dòng)商用存儲(chǔ)器芯片、構(gòu)建芯片間的高性能接口、創(chuàng)新型節(jié)電模式，這些只是高性能、低功耗、低成本 Spartan-6 FPGA 解決諸多問(wèn)題的一部分。
上傳時(shí)間： 2013-11-13
上傳用戶：bibirnovis
研究了一種采用FPGA將高清數(shù)字電視信號(hào)轉(zhuǎn)換為標(biāo)清數(shù)字電視信號(hào)的方法,利用重采樣等技術(shù)降低了圖像中每行的有效像素和垂直行,完成了HD-SDI到SD-SDI的下變換。設(shè)計(jì)實(shí)現(xiàn)簡(jiǎn)單,目前已運(yùn)用于實(shí)際工程當(dāng)中。
上傳時(shí)間： 2014-11-29
上傳用戶：mickey008
Xilinx FPGAs require at least two power supplies: VCCINTfor core circuitry and VCCO for I/O interface. For the latestXilinx FPGAs, including Virtex-II Pro, Virtex-II and Spartan-3, a third auxiliary supply, VCCAUX may be needed. Inmost cases, VCCAUX can share a power supply with VCCO.The core voltages, VCCINT, for most Xilinx FPGAs, rangefrom 1.2V to 2.5V. Some mature products have 3V, 3.3Vor 5V core voltages. Table 1 shows the core voltagerequirement for most of the FPGA device families. TypicalI/O voltages (VCCO) vary from 1.2V to 3.3V. The auxiliaryvoltage VCCAUX is 2.5V for Virtex-II Pro and Spartan-3, andis 3.3V for Virtex-II.
上傳時(shí)間： 2013-10-22
上傳用戶：liu999666
Xilinx Next Generation 28 nm FPGA Technology Overview Xilinx has chosen 28 nm high-κ metal gate (HKMG) highperformance,low-power process technology and combined it with a new unified ASMBL™ architecture to create a new generation of FPGAs that offer lower power and higher performance. These devices enable unprecedented levels of integration and bandwidth and provide system architects and designers a fully programmable alternative to ASSPs and ASICs.
上傳時(shí)間： 2014-12-28
上傳用戶：zhang97080564
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