In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digItal designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.
標簽：
Efficient
Verilog
digItal
Coding
上傳時間：
2013-11-22
上傳用戶：han_zh
