C++ Algorithms for digItal Signal Processing 第4章 濾波器程序
標(biāo)簽： Algorithms Processing digItal Signal
上傳時間： 2013-08-01
上傳用戶：eeworm
·[時鐘書籍]digItal Clocks for Synchronization and Communications
標(biāo)簽： nbsp Synchronization Communications digItal
上傳時間： 2013-05-24
上傳用戶：tgeyangjh
·[測試書籍]ESSENTIALS OF ELECTRONIC TESTING FOR digItal, MEMORY AND MIXED-SIGNAL VLSI CIRCUITS
標(biāo)簽： nbsp ESSENTIALS ELECTRONIC digItal
上傳時間： 2013-07-21
上傳用戶：euroford
·Verilog HDL: A Guide to digItal Design and
標(biāo)簽： nbsp Verilog digItal Design
上傳時間： 2013-04-24
上傳用戶：誰偷了我的麥兜
·Stanford&IBM牛人經(jīng)典之作 - digItal Control of Dynamic SystemsEditorial ReviewsProduct DescriptionThis well-respected, market-leading text discusses the use of digItal computers in the real-time co
標(biāo)簽： nbsp Hardcover digItal Control
上傳時間： 2013-07-31
上傳用戶：cuiyashuo
digItal Down Converter Design based on FPGA.
標(biāo)簽： Converter digItal Design based
上傳時間： 2013-08-13
上傳用戶：CSUSheep
直接數(shù)字頻率合成（Direct digItal Fraquency Synthesis,即DDFS，一般簡稱DDS）是從相位概念出發(fā)直接合成所需要波形的一種新的頻率合成技術(shù)。
標(biāo)簽： Fraquency Synthesis digItal Direct
上傳時間： 2013-08-27
上傳用戶：wpt
My thesis entitled \"fpga digItal clock,\" immature, to enlighten
上傳時間： 2013-08-31
上傳用戶：smallfish
Fpga Implementation Of digItal Timing Recovery In Software Radio Receiver
標(biāo)簽： Implementation Recovery Receiver Software
上傳時間： 2013-09-05
上傳用戶：panpanpan
In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digItal designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.
標(biāo)簽： Efficient Verilog digItal Coding
上傳時間： 2013-11-22
上傳用戶：han_zh
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