two counters pick up data from two encoders.
標(biāo)簽： two counters encoders pick
上傳時(shí)間： 2013-12-16
上傳用戶：xymbian
The CD4020BC, CD4060BC are 14-stage ripple carrybinary counters, and the CD4040BC is a 12-sta
標(biāo)簽： 4040 CMOS 二進(jìn)制計(jì) 分頻器
上傳時(shí)間： 2013-05-15
上傳用戶：ajaxmoon
英文描述： Synchronous Up/Down Decade counters(single clock line) 中文描述： 同步向上/向下十年計(jì)數(shù)器（單時(shí)鐘線）
上傳時(shí)間： 2013-06-18
上傳用戶：haohaoxuexi
S3C8-SERIESMCU 三星的SAM8RC系列8位單片機(jī)向用戶提供了高效快速的CPU，豐富的外圍接口，以及各種大小的可編程ROM。 它的地址/數(shù)據(jù)總線結(jié)構(gòu)和位可編程I/O口為用戶提供了一個(gè)靈活的編程環(huán)境，能夠滿足不同用戶對(duì)存儲(chǔ)器和I/O口的不同要求。同時(shí)，具有可選工作模式的Timer/counters可支持實(shí)時(shí)操作。
標(biāo)簽： S3F84B8 CMOS MCU 用戶手冊(cè)
上傳時(shí)間： 2014-07-12
上傳用戶：農(nóng)藥鋒6
各種功能的計(jì)數(shù)器實(shí)例（VHDL源代碼）:ENTITY counters IS PORT ( d : IN INTEGER RANGE 0 TO 255; clk : IN BIT; clear : IN BIT; ld : IN BIT; enable : IN BIT; up_down : IN BIT; qa : OUT INTEGER RANGE 0 TO 255; qb : OUT INTEGER RANGE 0 TO 255; qc : OUT INTEGER RANGE 0 TO 255; qd : OUT INTEGER RANGE 0 TO 255; qe : OUT INTEGER RANGE 0 TO 255; qf : OUT INTEGER RANGE 0 TO 255; qg : OUT INTEGER RANGE 0 TO 255; qh : OUT INTEGER RANGE 0 TO 255; qi : OUT INTEGER RANGE 0 TO 255;
標(biāo)簽： VHDL 計(jì)數(shù)器 源代碼
上傳時(shí)間： 2014-11-30
上傳用戶：半熟1994
This Application Note covers the basics of how to use Verilog as applied to ComplexProgrammable Logic Devices. Various combinational logic circuit examples, such asmultiplexers, decoders, encoders, comparators and adders are provided. Synchronous logiccircuit examples, such as counters and state machines are also provided.
標(biāo)簽： Verilog XAPP CPLD 143
上傳時(shí)間： 2013-11-11
上傳用戶：y13567890
各種功能的計(jì)數(shù)器實(shí)例（VHDL源代碼）:ENTITY counters IS PORT ( d : IN INTEGER RANGE 0 TO 255; clk : IN BIT; clear : IN BIT; ld : IN BIT; enable : IN BIT; up_down : IN BIT; qa : OUT INTEGER RANGE 0 TO 255; qb : OUT INTEGER RANGE 0 TO 255; qc : OUT INTEGER RANGE 0 TO 255; qd : OUT INTEGER RANGE 0 TO 255; qe : OUT INTEGER RANGE 0 TO 255; qf : OUT INTEGER RANGE 0 TO 255; qg : OUT INTEGER RANGE 0 TO 255; qh : OUT INTEGER RANGE 0 TO 255; qi : OUT INTEGER RANGE 0 TO 255;
標(biāo)簽： VHDL 計(jì)數(shù)器 源代碼
上傳時(shí)間： 2013-10-09
上傳用戶：松毓336
vhdl程序源代碼，包括Combinational Logic counters Shift Registers Memory State Machines Registers Systems ADC and DAC Arithmetic等
上傳時(shí)間： 2013-12-26
上傳用戶：363186
Features • Compatible with MCS-51® Products • 8K Bytes of In-System Programmable (ISP) Flash Memory – Endurance: 1000 Write/Erase Cycles • 4.0V to 5.5V Operating Range • Fully Static Operation: 0 Hz to 33 MHz • Three-level Program Memory Lock • 256 x 8-bit Internal RAM • 32 Programmable I/O Lines • Three 16-bit Timer/counters • Eight Interrupt Sources • Full Duplex UART Serial Channel • Low-power Idle and Power-down Modes • Interrupt Recovery from Power-down Mode • Watchdog Timer • Dual Data Pointer • Power-off Flag
標(biāo)簽： 8226 Programmable Compatible In-System
上傳時(shí)間： 2015-06-27
上傳用戶：dianxin61
The last step in training phase is refinement of the clusters found above. Although DynamicClustering counters all the basic k-means disadvantages, setting the intra-cluster similarity r may require experimentation. Also, a cluster may have a lot in common with another, i.e., sequences assigned to it are as close to it as they are to another cluster. There may also be denser sub-clusters within the larger ones.
標(biāo)簽： DynamicClusteri refinement Although clusters
上傳時(shí)間： 2014-01-04
上傳用戶：watch100
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