/*SPI規(guī)范：Data is always clocked into the device on the rising edge of SCK a-*/ /* nd clocked out of the device on the falling edge of SCK.All instruction-*/ /* s,addresses and data are transferred with the most significant bit(MSB) */ /* first.
標(biāo)簽： clocked the always device
上傳時(shí)間： 2016-02-19
上傳用戶：遠(yuǎn)遠(yuǎn)ssad
The TMS320VC5506/C5507/C5509A USB peripherals can be clocked from either the USB APLL or the USB DPLL. Since the APLL is inherently more noise tolerant and has less long-term jitter than the DPLL, it is recommended that you switch to it for any USB operations.
標(biāo)簽： USB peripherals the clocked
上傳時(shí)間： 2014-01-01
上傳用戶：yuzsu
This example shows how to update at regulate period the WWDG counter using theEarly Wakeup interrupt (EWI). The WWDG timeout is set to 262ms, refresh window set to 41h and the EWI isenabled. When the WWDG counter reaches 40h the EWI is generated and in the WWDGISR the counter is refreshed to prevent a WWDG reset and led connected to PC.07is toggled.The EXTI line9 is connected to PB.09 pin and configured to generate an interrupton falling edge.In the NVIC, EXTI line9 to 5 interrupt vector is enabled with priority equal to 0and the WWDG interrupt vector is enabled with priority equal to 1 (EXTI IT > WWDG IT). The EXTI Line9 will be used to simulate a software failure: once the EXTI line9event occurs (by pressing Key push-button on EVAL board) the correspondent interruptis served, in the ISR the led connected to PC.07 is turned off and the EXTI line9pending bit is not cleared. So the CPU will execute indefinitely EXTI line9 ISR andthe WWDG ISR will never be entered(WWDG counter not updated). As result, when theWWDG counter falls to 3Fh the WWDG reset occurs.If the EXTI line9 event don抰 occurs the WWDG counter is indefinitely refreshed inthe WWDG ISR which prevent from WWDG reset. If the WWDG reset is generated, after resuming from reset a led connected to PC.06is turned on. In this example the system is clocked by the HSE(8MHz).
上傳時(shí)間： 2013-11-11
上傳用戶：gundamwzc
計(jì)數(shù)器 鎖存器 12位寄存器 帶load，clr等功能的寄存器 雙向腳（clocked bidirectional pin） 一個(gè)簡單的狀態(tài)機(jī) 一個(gè)同步狀態(tài)機(jī) 用狀態(tài)機(jī)設(shè)計(jì)的交通燈控制器 數(shù)據(jù)接口 一個(gè)簡單的UART 測試向量（Test Bench）舉例： 加法器源程序 相應(yīng)加法器的測試向量test bench）
標(biāo)簽： load 計(jì)數(shù)器 位寄存器 鎖存器
上傳時(shí)間： 2014-01-16
上傳用戶：bjgaofei
// This program measures the voltage on an external ADC input and prints the // result to a terminal window via the UART. // // The system is clocked using the internal 24.5MHz oscillator. // Results are printed to the UART from a loop with the rate set by a delay // based on Timer 2. This loop periodically reads the ADC value from a global // variable, Result.
標(biāo)簽： the measures external program
上傳時(shí)間： 2013-12-27
上傳用戶：trepb001
vhdl編寫，8b—10b 編解碼器設(shè)計(jì) Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous clocked inputs (latched on each clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding Asynchronous active high reset initializes all logic Encoded data output 10-bit parallel encoded output valid 1 clock later Decoder: 8b/10b Decoder (file: 8b10b_dec.vhd) Synchronous clocked inputs (latched on each clock rising edge) 10-bit parallel encoded data input Asynchronous active high reset initializes all logic Decoded data, disparity and KO outputs 8-bit parallel unencoded output valid 1 clock later
上傳時(shí)間： 2016-05-05
上傳用戶：gundamwzc
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