In August of 1992 LTC published Application Note 49,
“Illumination Circuitry for Liquid Crystal Displays.” One
notable aspect of this event is that it generated more
response than all previous LTC application notes combined.
This level of interest, along with significant performance
advances since AN-49’s appearance, justifies
further discussion of LCD backlighting circuitry.
NXP Semiconductor designed the LPC2400 microcontrollers around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded Trace. The LPC2400 microcontrollers have 512 kB of on-chip high-speedFlash memory. This Flash memory includes a special 128-bit wide memory interface andaccelerator architecture that enables the CPU to execute sequential instructions fromFlash memory at the maximum 72 MHz system clock rate. This feature is available onlyon the LPC2000 ARM Microcontroller family of products. The LPC2400 can execute both32-bit ARM and 16-bit Thumb instructions. Support for the two Instruction Sets meansEngineers can choose to optimize their application for either performance or code size atthe sub-routine level. When the core executes instructions in Thumb state it can reducecode size by more than 30 % with only a small loss in performance while executinginstructions in ARM state maximizes core performance.
Virtex-5, Spartan-DSP FPGAs Application Note
This application note demonstrates how efficient implementations of Digital Up Converters(DUC) and Digital Down Converters (DDC) can be done by leveraging the Xilinx DSP IPportfolio for increased productivity and reduced time to development. Step-by-step instruction is given on how to perform system-level trade off analysis and develop the most efficient FPGA implementation, thus allowing engineers a flexible, low-cost and low-power alternative to ASSP technologies.
The PCA9517 is a CMOS integrated circuit that provides level shifting between lowvoltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I2C-bus or SMBus applications.While retaining all the operating modes and features of the I2C-bus system during thelevel shifts, it also permits extension of the I2C-bus by providing bidirectional buffering forboth the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF. Usingthe PCA9517 enables the system designer to isolate two halves of a bus for both voltageand capacitance. The SDA and SCL pins are over voltage tolerant and arehigh-impedance when the PCA9517 is unpowered.
The PCA9519 is a 4-channel level translating I2C-bus/SMBus repeater that enables theprocessor low voltage 2-wire serial bus to interface with standard I2C-bus or SMBus I/O.While retaining all the operating modes and features of the I2C-bus system during thelevel shifts, it also permits extension of the I2C-bus by providing bidirectional buffering forboth the data (SDA) and the clock (SCL) lines, thus enabling the I2C-bus or SMBusmaximum capacitance of 400 pF on the higher voltage side. The SDA and SCL pins areover-voltage tolerant and are high-impedance when the PCA9519 is unpowered.
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
CAN與RS232轉換節點的設計與實現
介紹將CAN總線接口與RS232總線接口相互轉換的設計方法和2種總線電平轉換關系，實現CAN總線與各模塊的接口設計，制定了相應的軟硬件設計方案，并給出軟件設計流程圖以及部分硬件設計原理圖。為CAN總線與RS232總線互聯提供了一種方法，對CAN總線與RS232總線接口設備的互聯和廣泛應用的實現具有重要意義。關鍵詞：CAN總線；RS-232總線；串行通信Design and Realization of CAN and RS232 Transformation NodeZHOU Wei, CHENG Xiao-hong(Information Institute, Wuhan University of Technology, Wuhan 430070)【Abstract】This paper introduces one design method of the CAN bus interface and the RS232 bus interface interconversion, emphasizes two kindof bus level transformation relations, realizes the CAN bus and various modules connection design, formulates the design proposal of correspondingsoftware and hardware, and gives the flow chart of software design as well as the partial schematic diagram of hardware design. It providesonemethod for the CAN bus and the RS232 bus interconnection, has the vital significance to widespread application realization of the CAN busand theRS232 bus interface equipment interconnection.【Key words】CAN bus; RS-232 bus; serial communication
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html
Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture
The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.
The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.
Some of the UltraScale architecture breakthroughs include:
• Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%
• Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability
• Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization
• 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard
• Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets
• Greatly enhanced DSP and packet handling
The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
